EPM570T100C5N - MAX II 570 LE CPLD, 100-TQFP | Intel (Altera)
料号： EPM570T100C5N ✓ 量产中| 数量 | 单价 | 小计 |
|---|---|---|
| 1 | $16.55 | $16.55 |
| 10 | $14.9 | $149.00 |
| 100 | $13.1 | $1,310.00 |
| 500 | $11.45 | $5,725.00 |
| 1,000 | $10.2 | $10,200.00 |
EPM570T100C5N 概述
A CPLD (Complex Programmable Logic Device) is a non-volatile digital IC that combines multiple PLA-like macrocell blocks on a single die with on-chip Flash configuration memory, providing instant-on logic at power-up without an external boot device. CPLDs sit in the programmable-logic hierarchy above discrete glue logic and below FPGAs, offering deterministic timing, low power, and pin-configurable I/O for bus decoding, state-machine, and interface-bridging tasks.
Key features include 8 Kbits of user Flash memory, in-system programmability (ISP) through IEEE 1149.1 JTAG, MultiVolt I/O supporting 1.5 V / 1.8 V / 2.5 V / 3.3 V interface levels, and a low-power standby mode. The on-chip voltage regulator accepts a single 3.3 V supply and generates the internal core voltage, simplifying board design. The MAX II family is targeted at cost-sensitive glue-logic, bus-bridge, and power-sequencing functions where FPGAs are overkill.
From an architecture perspective, the device uses a Logic Array Block (LAB) structure with 16 macrocells per LAB, an enhanced interconnect matrix, and a Joint Test Action Group (JTAG) interface compliant with IEEE Std 1149.1. The 8-Kbit user Flash can hold configuration revision data, serial numbers, or small lookup tables, eliminating the need for an external EEPROM in many designs.
Typical applications include I/O expansion and bus decoding for microcontrollers, FPGA/CPLD configuration and power-up sequencing, LED driving and PWM generation, retro-computing glue logic, glue logic for ASIC/ASSP replacement, and JTAG-controlled board-test fixtures. Designers use the EPM570T100C5N where deterministic pin-to-pin timing, instant-on behavior, and small board area are critical.
A key design consideration is the MultiVolt I/O bank configuration: each I/O bank can independently mix 1.5 V, 1.8 V, 2.5 V, and 3.3 V signaling levels provided the VCCIO rails are correctly grouped. Designers should consult the device pinout to plan bank assignments before PCB layout, since incorrect bank partitioning can lead to level-shifter rework.
This page synthesizes distributor pricing, drop-in same-package alternatives, and practical design considerations not consolidated in any single manufacturer datasheet.
直接替换替代料： EPM570T100C5N ——相同封装，引脚兼容。需要 PCB 改动的不同封装料号已排除。
本系列中的变体
可与以下型号直接替换的同系列型号： EPM570T100C5N （相同外形与封装尺寸） ——差异在于 Package, Operating Temperature, Process Technology, Programming Interface, RoHS Status.
快速对比工具——选择替代料号进行并排对比：
EPM570T100C4N
✅ 直接替换✓ 有现货
$9.05 / 个
查看数据手册 →EPM570T100A5N
✅ 直接替换✓ 有现货
$6.72 / 个
查看数据手册 →EPM570T100I5N
✅ 直接替换✓ 有现货
$12.49 / 个
查看数据手册 →EPM570T100C3N
✅ 直接替换✓ 有现货
$8.1 / 个
查看数据手册 →EPM570M100C5N
✅ 直接替换✓ 有现货
$11.85 / 个
查看数据手册 →EPM570T100C5N 最大额定值与电气特性
| Series | MAX II |
| Family | CPLD - MAX II |
| Logic Elements (LE) | 570 |
| Macrocells | 440 |
| User I/Os | 76 |
| User Flash Memory | 8 Kbit |
| Process Technology | 0.18 µm 6-layer-metal Flash |
| Internal Performance | 201.1 MHz |
| 电源电压 | 2.5 V / 3.3 V |
| 工作温度 | 0 °C to +85 °C (commercial) |
| 封装 | 100-pin TQFP (T100) |
| 安装类型 | Surface Mount |
| Programming Interface | JTAG (IEEE 1149.1) / ISP |
| I/O Standards | 1.5 V / 1.8 V / 2.5 V / 3.3 V MultiVolt |
| RoHS 状态 | Compliant |
EPM570T100C5N 引脚配置
| 引脚 1 | I/O — General-purpose user I/O pin |
| 引脚 2 | I/O — General-purpose user I/O pin |
| 引脚 3 | I/O — General-purpose user I/O pin |
| 引脚 4 | I/O — General-purpose user I/O pin |
| 引脚 5 | I/O — General-purpose user I/O pin |
| 引脚 6 | I/O — General-purpose user I/O pin |
| 引脚 7 | VCCIO1 — I/O bank 1 supply voltage |
| 引脚 8 | I/O — General-purpose user I/O pin |
| 引脚 9 | I/O — General-purpose user I/O pin |
| 引脚 10 | I/O — General-purpose user I/O pin |
| 引脚 11 | I/O — General-purpose user I/O pin |
| 引脚 12 | GND — Ground |
| 引脚 13 | I/O — General-purpose user I/O pin |
| 引脚 14 | I/O — General-purpose user I/O pin |
| 引脚 15 | I/O — General-purpose user I/O pin |
| 引脚 16 | I/O — General-purpose user I/O pin |
| 引脚 17 | I/O — General-purpose user I/O pin |
| 引脚 18 | I/O — General-purpose user I/O pin |
| 引脚 19 | I/O — General-purpose user I/O pin |
| 引脚 20 | I/O — General-purpose user I/O pin |
| 引脚 21 | GND — Ground |
| 引脚 22 | I/O — General-purpose user I/O pin |
| 引脚 23 | I/O — General-purpose user I/O pin |
| 引脚 24 | I/O — General-purpose user I/O pin |
| 引脚 25 | I/O — General-purpose user I/O pin |
| 引脚 26 | I/O — General-purpose user I/O pin |
| 引脚 27 | I/O — General-purpose user I/O pin |
| 引脚 28 | VCCIO1 — I/O bank 1 supply voltage |
| 引脚 29 | I/O — General-purpose user I/O pin |
| 引脚 30 | I/O — General-purpose user I/O pin |
| 引脚 31 | I/O — General-purpose user I/O pin |
| 引脚 32 | I/O — General-purpose user I/O pin |
| 引脚 33 | I/O — General-purpose user I/O pin |
| 引脚 34 | I/O — General-purpose user I/O pin |
| 引脚 35 | I/O — General-purpose user I/O pin |
| 引脚 36 | I/O — General-purpose user I/O pin |
| 引脚 37 | GND — Must be connected to GND (per EPM570-specific pinout) |
| 引脚 38 | TDI — JTAG Test Data In |
| 引脚 39 | VCCIO2 — Must be connected to 3.3V (per EPM570-specific pinout) |
| 引脚 40 | TMS — JTAG Test Mode Select |
| 引脚 41 | TCK — JTAG Test Clock |
| 引脚 42 | TDO — JTAG Test Data Out |
| 引脚 43 | I/O — General-purpose user I/O pin |
| 引脚 44 | I/O — General-purpose user I/O pin |
| 引脚 45 | I/O — General-purpose user I/O pin |
| 引脚 46 | I/O — General-purpose user I/O pin |
| 引脚 47 | I/O — General-purpose user I/O pin |
| 引脚 48 | I/O — General-purpose user I/O pin |
| 引脚 49 | I/O — General-purpose user I/O pin |
| 引脚 50 | I/O — General-purpose user I/O pin |
| 引脚 51 | GND — Ground |
| 引脚 52 | I/O — General-purpose user I/O pin |
| 引脚 53 | I/O — General-purpose user I/O pin |
| 引脚 54 | I/O — General-purpose user I/O pin |
| 引脚 55 | I/O — General-purpose user I/O pin |
| 引脚 56 | I/O — General-purpose user I/O pin |
| 引脚 57 | I/O — General-purpose user I/O pin |
| 引脚 58 | I/O — General-purpose user I/O pin |
| 引脚 59 | I/O — General-purpose user I/O pin |
| 引脚 60 | I/O — General-purpose user I/O pin |
| 引脚 61 | VCCIO2 — I/O bank 2 supply voltage |
| 引脚 62 | I/O — General-purpose user I/O pin |
| 引脚 63 | I/O — General-purpose user I/O pin |
| 引脚 64 | I/O — General-purpose user I/O pin |
| 引脚 65 | I/O — General-purpose user I/O pin |
| 引脚 66 | I/O — General-purpose user I/O pin |
| 引脚 67 | I/O — General-purpose user I/O pin |
| 引脚 68 | I/O — General-purpose user I/O pin |
| 引脚 69 | I/O — General-purpose user I/O pin |
| 引脚 70 | I/O — General-purpose user I/O pin |
| 引脚 71 | GND — Ground |
| 引脚 72 | I/O — General-purpose user I/O pin |
| 引脚 73 | I/O — General-purpose user I/O pin |
| 引脚 74 | I/O — General-purpose user I/O pin |
| 引脚 75 | I/O — General-purpose user I/O pin |
| 引脚 76 | I/O — General-purpose user I/O pin |
| 引脚 77 | I/O — General-purpose user I/O pin |
| 引脚 78 | I/O — General-purpose user I/O pin |
| 引脚 79 | I/O — General-purpose user I/O pin |
| 引脚 80 | I/O — General-purpose user I/O pin |
| 引脚 81 | VCCIO3 — I/O bank 3 supply voltage |
| 引脚 82 | I/O — General-purpose user I/O pin |
| 引脚 83 | I/O — General-purpose user I/O pin |
| 引脚 84 | I/O — General-purpose user I/O pin |
| 引脚 85 | I/O — General-purpose user I/O pin |
| 引脚 86 | I/O — General-purpose user I/O pin |
| 引脚 87 | I/O — General-purpose user I/O pin |
| 引脚 88 | VCCIO3 — Must be connected to 3.3V (per EPM570-specific pinout) |
| 引脚 89 | I/O — General-purpose user I/O pin |
| 引脚 90 | GND — Must be connected to GND (per EPM570-specific pinout) |
| 引脚 91 | I/O — General-purpose user I/O pin |
| 引脚 92 | I/O — General-purpose user I/O pin |
| 引脚 93 | I/O — General-purpose user I/O pin |
| 引脚 94 | I/O — General-purpose user I/O pin |
| 引脚 95 | I/O — General-purpose user I/O pin |
| 引脚 96 | VCCINT — Internal core supply voltage (3.3V) |
| 引脚 97 | I/O — General-purpose user I/O pin |
| 引脚 98 | I/O — General-purpose user I/O pin |
| 引脚 99 | I/O — General-purpose user I/O pin |
| 引脚 100 | I/O — General-purpose user I/O pin |
典型应用
EPM570T100C5N 适用于 6 应用s: Microcontroller I/O Expansion and Bus Decoding, FPGA Configuration and Power Sequencing, Retro-Computing and Hobby Glue Logic, LED Driving and PWM Generation, ASIC/ASSP Replacement for EOL Parts, JTAG-Based Board Test and Boundary Scan.
Microcontroller I/O Expansion and Bus Decoding
The EPM570T100C5N's 570 logic elements and 76 user I/Os make it ideal for expanding microcontroller I/O counts and decoding address/data buses. Its deterministic pin-to-pin propagation delays and MultiVolt I/O allow direct interfacing with 3.3 V MCUs and 1.8 V peripherals in the same design. Instant-on non-volatile configuration eliminates boot-time delays, which is critical for real-time control loops where the MCU expects the CPLD's decoded chip-selects to be valid at reset release. The 8-Kbit user Flash can store revision IDs or serial numbers for board identification.
推荐
FPGA Configuration and Power Sequencing
The EPM570T100C5N is widely used as a configuration watchdog and power sequencer for FPGAs and processors. Its JTAG interface can chain to downstream FPGAs for boundary-scan testing, while its programmable logic can enforce power-up/power-down sequencing across multiple rails. The 440 macrocells easily handle sequencing for 4-8 voltage rails, and the instant-on Flash-based configuration means the CPLD is alive before the main FPGA begins its configuration load, ready to gate resets and monitor PGOOD signals.
推荐
Retro-Computing and Hobby Glue Logic
Retro-computing enthusiasts use the EPM570T100C5N to replace vintage 7400-series TTL glue logic with a single re-programmable chip. Its 570 logic elements and 76 I/Os can implement dozens of legacy 74xx functions in one device, simplifying board layout and reducing BOM count. The TQFP-100 package is breadboard-friendly with breakout boards, and the JTAG interface allows ISP reprogramming without removing the chip. Commercial temperature grade is sufficient for typical indoor hobby use, and the instant-on behavior matches the deterministic timing vintage CPUs expect.
推荐
LED Driving and PWM Generation
The EPM570T100C5N generates multiple independent PWM channels for LED dimming, motor control, or fan speed regulation. Each macrocell can be configured as a free-running counter with programmable duty cycle, and the 201.1 MHz internal performance supports PWM frequencies well above the audible band to avoid motor whine. The MultiVolt I/O banks drive LED strings directly at 3.3 V or 5 V logic levels, and the 76 user I/Os can independently control up to 38 LED channels with current-limiting resistors.
推荐
ASIC/ASSP Replacement for EOL Parts
Designers use the EPM570T100C5N as a drop-in functional replacement for obsolete ASICs or ASSPs in long-lifecycle products. Because the device is re-programmable, last-minute logic changes do not require a new silicon spin, accelerating time-to-market. The 440 macrocells and 76 I/Os cover most glue-logic integration tasks, while the commercial-grade temperature range suits industrial, medical, and consumer products. The MAX II family's 0.18 µm Flash process provides excellent data retention (>20 years) for field-deployed equipment.
推荐
JTAG-Based Board Test and Boundary Scan
The EPM570T100C5N implements IEEE 1149.1 JTAG boundary-scan for production board test, allowing cluster testing of nets that are otherwise inaccessible with bed-of-nails fixtures. Its JTAG interface can be chained with other JTAG-compliant ICs on the board, and the on-chip user Flash can store board-test firmware that runs at power-on. The TQFP-100 package exposes all JTAG signals (TCK, TMS, TDI, TDO) plus the 76 user I/Os as boundary-scan cells, providing extensive fault coverage for shorts, opens, and stuck-at defects.
推荐
推荐产品汇总
工程参考数据： EPM570T100C5N ——对比、设计指导和合规信息。
选型指南
与替代料对比
| 参数 | 本产品 | EPM570T100C4N | EPM570T100A5N | EPM570T100I5N | EPM570T100C3N | EPM570M100C5N |
|---|---|---|---|---|---|---|
| Package | TQFP-100 | TQFP-100 - same | TQFP-100 - same | TQFP-100 - same | TQFP-100 - same | TQFP-100 - same |
| Brand | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) |
| Logic Elements | 570 | 570 | 570 | 570 | 570 | 570 |
| Macrocells | 440 | 440 | 440 | 440 | 440 | 440 |
| Speed Grade | C5 (fastest) | C4 (slower) | A5 (alternate) | I5 (industrial) | C3 (slowest) | C5 (equivalent) |
| Operating Temperature | 0C to +85C (commercial) | 0C to +85C (commercial) | 0C to +85C (commercial) | -40C to +100C (industrial) | 0C to +85C (commercial) | 0C to +85C (commercial) |
| User I/Os | 76 | 76 | 76 | 76 | 76 | 76 |
关键差异点
- Fastest speed grade in TQFP-100 footprint （对比 EPM570T100C4N)
- Commercial temperature grade at lowest price （对比 EPM570T100I5N)
- 570 logic elements vs smaller pin-compatible variants （对比 EPM240T100C5N)
设计说明
The EPM570T100C5N requires a stable 3.3 V supply on VCCINT (pin 96) and separate VCCIO rails for each I/O bank (VCCIO1, VCCIO2, VCCIO3). Decouple each VCC rail with a 0.1 µF ceramic capacitor placed as close to the pin as possible, plus a bulk 10 µF tantalum or polymer capacitor on the 3.3 V rail. For MultiVolt operation, each VCCIO rail can be independently set to 1.5 V, 1.8 V, 2.5 V, or 3.3 V to match downstream devices; verify bank assignments in the Quartus pin planner before PCB layout. Pins 37 and 90 MUST be tied to GND; pins 39 and 88 MUST be tied to 3.3 V for the EPM570 die in this package.
Route JTAG signals (TCK, TMS, TDI, TDO) with 50 Ω controlled impedance and keep trace lengths under 50 mm to avoid signal-integrity issues at high programming clock rates. Place the JTAG header or test pad on the board edge for bed-of-nails fixture access. The TQFP-100 footprint has 0.5 mm pitch leads; use a PCB land pattern with at least 0.2 mm solder mask expansion and consider via-in-pad for thermal dissipation. Keep high-speed I/O traces short and impedance-matched to minimize reflections.
Do not confuse the EPM570T100C5N with the EPM240T100C5N - both share the same TQFP-100 package but the EPM240 uses pins 37, 39, 88, 90 as I/O, while on the EPM570 those pins have fixed tie-off requirements (37/90 to GND, 39/88 to 3.3 V). Substituting one for the other without re-routing will result in incorrect JTAG or power behavior. Always verify the device ID readback in Quartus Programmer after programming to confirm the correct silicon is responding.
合规信息
RoHS compliant per Altera/Intel product page. Not AEC-Q100 qualified - MAX II CPLDs are not designed for automotive AEC-Q100 applications; consult Intel automotive-grade MAX V or Cyclone families for AEC-Q100 needs.