A42MX24-PLG84M - 36K Gate FPGA, 84-PLCC | Microchip
料号： A42MX24-PLG84M ✓ 量产中| 数量 | 单价 | 小计 |
|---|---|---|
| 1 | $1403.42 | $1,403.42 |
| 10 | $1333.25 | $13,332.50 |
| 100 | $1265 | $126,500.00 |
| 500 | $1202.5 | $601,250.00 |
| 1,000 | $1142.38 | $1,142,380.00 |
A42MX24-PLG84M 概述
A field programmable gate array (FPGA) is a semiconductor device containing configurable logic blocks and interconnects that designers program in the field. Within the programmable logic hierarchy, the MX family sits as a fuse-based, antifuse-style, non-volatile programmable logic platform - an alternative to CPLDs and standard-cell ASICs for glue logic, legacy PLD consolidation, and moderate-density control functions.
Key features include the MX 5.0V architecture with efficient routing, D-modules with wide-decode circuitry providing fast wide-input AND functions similar to CPLD architectures, and dual supply support (3.3V/5V). The 42MX family integrates legacy PLDs into a single low-cost device, reducing board area and component count in cost-sensitive systems.
Architecturally, A42MX24 combines C-modules (combinational), S-modules (sequential with registers), and D-modules (wide decode) arranged to balance logic density and fast decode paths. The antifuse-style non-volatile programming means the device configures instantly at power-up with no external boot PROM, improving system reliability and security compared to SRAM FPGAs.
Typical applications include industrial control and automation, legacy system redesign and BOM consolidation, glue logic integration, high-volume appliances, and military/aerospace upgrade programs where proven, radiation-tolerant-heritage programmable logic is valued.
Design consideration: verify speed grade and temperature suffix in the full ordering code, and confirm PLCC through-hole/socket mounting constraints early, since PLCC packaging differs from modern surface-mount QFP/BGA footprints.
直接替换替代料： A42MX24-PLG84M ——相同封装，引脚兼容。需要 PCB 改动的不同封装料号已排除。
本系列中的变体
可与以下型号直接替换的同系列型号： A42MX24-PLG84M （相同外形与封装尺寸） ——差异在于 Package, Family, Operating Temperature, System Gates, Speed Grade.
快速对比工具——选择替代料号进行并排对比：
A42MX24-3PLG84I
✅ 直接替换✓ 有现货
$43.5 / 个
查看数据手册 →A42MX24-2PLG84I
✅ 直接替换✓ 有现货
$55.4 / 个
查看数据手册 →A42MX24-3PLG84
✅ 直接替换✓ 有现货
$44.2 / 个
查看数据手册 →A42MX16-3PLG84I
✅ 直接替换✓ 有现货
$21.9 / 个
查看数据手册 →A42MX16-1PLG84I
✅ 直接替换✓ 有现货
$1 / 个
查看数据手册 →A42MX09-PLG84M
✅ 直接替换✓ 有现货
联系询价
查看数据手册 →A42MX24-PLG84M 最大额定值与电气特性
| Family | MX (42MX) |
| System Gates | 36000 gates |
| Logic Modules / Cells | 912 cells |
| Number of I/O | 72 |
| Technology | 0.45 um CMOS |
| 电源电压 | 3.3 V / 5 V |
| Core Voltage | 5 V |
| 封装 | 84-PLCC (PLG84) |
| 安装类型 | Surface Mount (PLCC J-Lead) |
| Programmability | Non-volatile, instantaneous power-up |
| D-Modules (Wide Decode) | Yes |
| Application | Single-chip ASIC alternative, legacy PLD integration |
A42MX24-PLG84M 引脚配置
| 引脚 1-10 | USER I/O — User input/output pins (distribution per datasheet PLG84 pin table) |
| 引脚 11 | VPP — Programming voltage (per MX family datasheet) |
| 引脚 12 | VCCI — I/O supply |
| 引脚 13-30 | USER I/O — User input/output pins (distribution per datasheet PLG84 pin table) |
| 引脚 31 | GND — Ground |
| 引脚 32-70 | USER I/O — User input/output pins (distribution per datasheet PLG84 pin table) |
| 引脚 71 | VCC — Core supply 5V |
| 引脚 72-84 | USER I/O / POWER — Remaining I/O and power pins (72 total user I/O per datasheet) |
典型应用
A42MX24-PLG84M 适用于 6 应用s: Industrial Control and Automation, Legacy System Redesign and BOM Consolidation, High-Volume Cost-Sensitive Systems, Aerospace and Defense Legacy Upgrades, Glue Logic and Bus Interface Integration, Prototype and Low-Volume Custom Logic.
Industrial Control and Automation
The A42MX24-PLG84M suits industrial control because its 5V-tolerant, 3.3V/5V mixed I/O connects directly to legacy 5V PLC backplanes without level shifters, and its 72 user I/O handles parallel sensor and actuator interfaces. Non-volatile configuration gives instant-on operation after power loss - important in factory equipment that must resume deterministically. D-module wide-decode circuitry implements fast address decoding for peripheral maps, while the 36K gates integrate multiple legacy 22V10-class PLDs into one device, cutting board area and BOM cost.
推荐
Legacy System Redesign and BOM Consolidation
For redesigning obsolete boards, the A42MX24-PLG84M consolidates legacy PLDs, glue logic, and PAL/GAL devices into a single 36K-gate, non-volatile FPGA. Its 0.45 um 5V architecture matches the electrical environment of 1980s-1990s systems, so no redesign of supply rails is needed. The 84-PLCC package is socketable, allowing field-upgradable or removable logic. This makes the MX family a low-risk drop-in consolidation platform that shortens redesign cycles while preserving the original design's timing behavior.
推荐
High-Volume Cost-Sensitive Systems
The MX family is explicitly positioned by Microchip as a high-volume platform for integrating legacy PLDs at low cost. The A42MX24-PLG84M's mature 0.45 um process yields low unit cost and stable long-run supply, and non-volatile programming removes the external configuration device that adds cost to SRAM FPGA builds. For appliances, meters, and controllers produced in hundreds of thousands of units, the single-chip solution reduces assembly, inventory, and test cost versus discrete PLD clusters.
推荐
Aerospace and Defense Legacy Upgrades
Actel MX devices carry long heritage in defense and aerospace programs where non-volatile, SEU-robust programming and long-lifecycle availability matter. The A42MX24-PLG84M lets program offices upgrade obsolete logic boards while keeping proven MX silicon. Instant-on configuration with no bitstream load avoids configuration vulnerabilities at power-up, and the wide industrial temperature variants (PLG84I suffix) support harsh environments. Verify program-specific screening requirements (mil-temp or flow variants) with Microchip before order placement.
推荐
Glue Logic and Bus Interface Integration
The A42MX24-PLG84M is optimized for glue logic: D-modules provide wide-input AND decode similar to CPLD architectures, delivering fast chip-select and address-decode functions for microprocessor buses. The 72 user I/O with 5V tolerance interfaces directly to 5V microcontrollers, SRAM, and peripherals. Integrating bus arbitration, wait-state generation, and I/O mapping into one 36K-gate device removes dozens of 74-series packages, shortening propagation paths and improving timing margin across the board.
推荐
Prototype and Low-Volume Custom Logic
Because the PLCC-84 package is socketable and the MX device is one-time programmable but instantly configured, the A42MX24-PLG84M fits prototype runs and low-volume products that need reliable custom logic without FPGA configuration-chain complexity. Designers using Libero/Microchip legacy MX toolchain can compile state machines, decoders, and data-path logic into 912 cells. For builds needing multiple iterations, socketing allows swapping programmed devices during debug and validation cycles.
推荐
推荐产品汇总
工程参考数据： A42MX24-PLG84M ——对比、设计指导和合规信息。
选型指南
与替代料对比
| 参数 | 本产品 | A42MX24-3PLG84I | A42MX24-2PLG84I | A42MX16-3PLG84I | A42MX09-PLG84M |
|---|---|---|---|---|---|
| Package | 84-PLCC (PLG84) | 84-PLCC (PLG84) - same | 84-PLCC (PLG84) - same | 84-PLCC (PLG84) - same | 84-PLCC (PLG84) - same |
| Brand | Microchip Technology (Microsemi) | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology |
| System Gates | 36000 | 36000 | 36000 | 24000 (16K class) | 9000 (9K class) |
| Supply Voltage | 3.3 V / 5 V | 3.3 V / 5 V | 3.3 V / 5 V | 3.3 V / 5 V | 3.3 V / 5 V |
| Temperature Range | Commercial (base suffix) | Industrial (I suffix) | Industrial (I suffix) | Industrial (I suffix) | Same suffix convention (M) |
关键差异点
- Full 36K gate density in 84-pin package （对比 A42MX16-3PLG84I)
- Faster timing option available （对比 A42MX24-2PLG84I)
- Non-volatile instant-on configuration （对比 SRAM-based FPGAs)
设计说明
The A42MX24 operates from a 5V core with 3.3V/5V I/O capability. Decouple each VCC/VCCI pin on the PLCC-84 with 0.1 uF ceramic capacitors placed as close to the supply pins as possible, plus one bulk 10 uF per rail. PLCC packages have longer internal lead paths than QFN/BGA, so distributed decoupling is essential to control ground bounce during simultaneous switching of the 72 I/O.
The 84-PLCC J-lead package can be surface mounted or socketed. If using a socket, account for additional lead inductance (roughly 1-2 nH per pin) which degrades signal integrity on fast edges and increases simultaneous-switching noise. For direct surface mounting, PLCC footprints per IPC-SM-782 geometry are recommended; verify land pattern against your fab's capability for J-lead inspection.
MX devices are one-time programmable - a design change requires a new device, so thoroughly validate the design in simulation and, if available, in-circuit emulation before programming production units. Also confirm the exact ordering code: speed grade (1/2/3), temperature (I/M/A suffixes), and package (PLG84) are all encoded in the suffix; mixing speed grades across a build creates AC timing inconsistency.
合规信息
Compliance data was not present in the provided verified web data; confirm RoHS/REACH status on the Microchip product page for the exact ordering code before purchase.
