A42MX24-PLG84M - 36K Gate FPGA, 84-PLCC | Microchip
MPN: A42MX24-PLG84M ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $1403.42 | $1,403.42 |
| 10 | $1333.25 | $13,332.50 |
| 100 | $1265 | $126,500.00 |
| 500 | $1202.5 | $601,250.00 |
| 1,000 | $1142.38 | $1,142,380.00 |
Drop-in alternatives for A42MX24-PLG84M — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
A42MX24-3PLG84I
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View Datasheet →A42MX24-2PLG84I
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View Datasheet →A42MX24-3PLG84
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View Datasheet →A42MX16-3PLG84I
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View Datasheet →A42MX16-1PLG84I
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View Datasheet →A42MX09-PLG84M
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View Datasheet →A42MX24-PLG84M Maximum Ratings & Electrical Characteristics
| Family | MX (42MX) |
| System Gates | 36000 gates |
| Logic Modules / Cells | 912 cells |
| Number of I/O | 72 |
| Technology | 0.45 um CMOS |
| Supply Voltage | 3.3 V / 5 V |
| Core Voltage | 5 V |
| Package | 84-PLCC (PLG84) |
| Mounting Type | Surface Mount (PLCC J-Lead) |
| Programmability | Non-volatile, instantaneous power-up |
| D-Modules (Wide Decode) | Yes |
| Operating Temperature | [DATA_NEEDED: operating temperature range] |
| Speed Grade | [DATA_NEEDED: speed grade suffix detail] |
| MSL Level | [DATA_NEEDED: MSL] |
| RoHS Status | [DATA_NEEDED: RoHS status] |
| Application | Single-chip ASIC alternative, legacy PLD integration |
A42MX24-PLG84M Pin Configuration
| Pin 1-10 | USER I/O — User input/output pins (distribution per datasheet PLG84 pin table) |
| Pin 11 | VPP — Programming voltage (per MX family datasheet) |
| Pin 12 | VCCI — I/O supply |
| Pin 13-30 | USER I/O — User input/output pins (distribution per datasheet PLG84 pin table) |
| Pin 31 | GND — Ground |
| Pin 32-70 | USER I/O — User input/output pins (distribution per datasheet PLG84 pin table) |
| Pin 71 | VCC — Core supply 5V |
| Pin 72-84 | USER I/O / POWER — Remaining I/O and power pins (72 total user I/O per datasheet) |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
A42MX24-PLG84M is suitable for 6 applications: Industrial Control and Automation, Legacy System Redesign and BOM Consolidation, High-Volume Cost-Sensitive Systems, Aerospace and Defense Legacy Upgrades, Glue Logic and Bus Interface Integration, Prototype and Low-Volume Custom Logic.
Industrial Control and Automation
The A42MX24-PLG84M suits industrial control because its 5V-tolerant, 3.3V/5V mixed I/O connects directly to legacy 5V PLC backplanes without level shifters, and its 72 user I/O handles parallel sensor and actuator interfaces. Non-volatile configuration gives instant-on operation after power loss - important in factory equipment that must resume deterministically. D-module wide-decode circuitry implements fast address decoding for peripheral maps, while the 36K gates integrate multiple legacy 22V10-class PLDs into one device, cutting board area and BOM cost.
Recommended
Legacy System Redesign and BOM Consolidation
For redesigning obsolete boards, the A42MX24-PLG84M consolidates legacy PLDs, glue logic, and PAL/GAL devices into a single 36K-gate, non-volatile FPGA. Its 0.45 um 5V architecture matches the electrical environment of 1980s-1990s systems, so no redesign of supply rails is needed. The 84-PLCC package is socketable, allowing field-upgradable or removable logic. This makes the MX family a low-risk drop-in consolidation platform that shortens redesign cycles while preserving the original design's timing behavior.
Recommended
High-Volume Cost-Sensitive Systems
The MX family is explicitly positioned by Microchip as a high-volume platform for integrating legacy PLDs at low cost. The A42MX24-PLG84M's mature 0.45 um process yields low unit cost and stable long-run supply, and non-volatile programming removes the external configuration device that adds cost to SRAM FPGA builds. For appliances, meters, and controllers produced in hundreds of thousands of units, the single-chip solution reduces assembly, inventory, and test cost versus discrete PLD clusters.
Recommended
Aerospace and Defense Legacy Upgrades
Actel MX devices carry long heritage in defense and aerospace programs where non-volatile, SEU-robust programming and long-lifecycle availability matter. The A42MX24-PLG84M lets program offices upgrade obsolete logic boards while keeping proven MX silicon. Instant-on configuration with no bitstream load avoids configuration vulnerabilities at power-up, and the wide industrial temperature variants (PLG84I suffix) support harsh environments. Verify program-specific screening requirements (mil-temp or flow variants) with Microchip before order placement.
Recommended
Glue Logic and Bus Interface Integration
The A42MX24-PLG84M is optimized for glue logic: D-modules provide wide-input AND decode similar to CPLD architectures, delivering fast chip-select and address-decode functions for microprocessor buses. The 72 user I/O with 5V tolerance interfaces directly to 5V microcontrollers, SRAM, and peripherals. Integrating bus arbitration, wait-state generation, and I/O mapping into one 36K-gate device removes dozens of 74-series packages, shortening propagation paths and improving timing margin across the board.
Recommended
Prototype and Low-Volume Custom Logic
Because the PLCC-84 package is socketable and the MX device is one-time programmable but instantly configured, the A42MX24-PLG84M fits prototype runs and low-volume products that need reliable custom logic without FPGA configuration-chain complexity. Designers using Libero/Microchip legacy MX toolchain can compile state machines, decoders, and data-path logic into 912 cells. For builds needing multiple iterations, socketing allows swapping programmed devices during debug and validation cycles.
Recommended
Recommended Products Summary
Engineering reference data for A42MX24-PLG84M — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | A42MX24-3PLG84I | A42MX24-2PLG84I | A42MX16-3PLG84I | A42MX09-PLG84M |
|---|---|---|---|---|---|
| Package | 84-PLCC (PLG84) | 84-PLCC (PLG84) - same | 84-PLCC (PLG84) - same | 84-PLCC (PLG84) - same | 84-PLCC (PLG84) - same |
| Brand | Microchip Technology (Microsemi) | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology |
| System Gates | 36000 | 36000 | 36000 | 24000 (16K class) | 9000 (9K class) |
| Logic Cells | 912 | 912 | 912 | [DATA_NEEDED] | [DATA_NEEDED] |
| User I/O | 72 | 72 | 72 | [DATA_NEEDED] | [DATA_NEEDED] |
| Supply Voltage | 3.3 V / 5 V | 3.3 V / 5 V | 3.3 V / 5 V | 3.3 V / 5 V | 3.3 V / 5 V |
| Speed Grade | [DATA_NEEDED: base speed grade] | Speed grade 3 (fastest) | Speed grade 2 | Speed grade 3 | [DATA_NEEDED] |
| Temperature Range | Commercial (base suffix) | Industrial (I suffix) | Industrial (I suffix) | Industrial (I suffix) | Same suffix convention (M) |
Key Differentiators
- Full 36K gate density in 84-pin package (vs A42MX16-3PLG84I)
- Faster timing option available (vs A42MX24-2PLG84I)
- Non-volatile instant-on configuration (vs SRAM-based FPGAs)
Design Notes
The A42MX24 operates from a 5V core with 3.3V/5V I/O capability. Decouple each VCC/VCCI pin on the PLCC-84 with 0.1 uF ceramic capacitors placed as close to the supply pins as possible, plus one bulk 10 uF per rail. PLCC packages have longer internal lead paths than QFN/BGA, so distributed decoupling is essential to control ground bounce during simultaneous switching of the 72 I/O.
The 84-PLCC J-lead package can be surface mounted or socketed. If using a socket, account for additional lead inductance (roughly 1-2 nH per pin) which degrades signal integrity on fast edges and increases simultaneous-switching noise. For direct surface mounting, PLCC footprints per IPC-SM-782 geometry are recommended; verify land pattern against your fab's capability for J-lead inspection.
MX devices are one-time programmable - a design change requires a new device, so thoroughly validate the design in simulation and, if available, in-circuit emulation before programming production units. Also confirm the exact ordering code: speed grade (1/2/3), temperature (I/M/A suffixes), and package (PLG84) are all encoded in the suffix; mixing speed grades across a build creates AC timing inconsistency.
Compliance Information
Compliance data was not present in the provided verified web data; confirm RoHS/REACH status on the Microchip product page for the exact ordering code before purchase.
