A42MX16-3PLG84I - 24K Gate MX FPGA, 84-PLCC | Microchip
MPN: A42MX16-3PLG84I ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $32.5 | $32.50 |
| 10 | $29.6 | $296.00 |
| 100 | $26.8 | $2,680.00 |
| 500 | $24.2 | $12,100.00 |
| 1,000 | $21.9 | $21,900.00 |
Drop-in alternatives for A42MX16-3PLG84I — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
A42MX16-3PLG84
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View Datasheet →A42MX16-2PLG84I
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View Datasheet →A42MX16-1PLG84I
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View Datasheet →A42MX16-2PLG84
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View Datasheet →A42MX24-3PLG84I
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View Datasheet →A42MX16-FPLG84
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View Datasheet →A42MX16-3PLG84I Maximum Ratings & Electrical Characteristics
| Family | MX (42MX) FPGA |
| System Gates | 24000 gates |
| Logic Cells | 608 cells |
| User I/O | 72 |
| Speed Grade | -3 |
| Toggle Rate | 142 MHz / 237 MHz |
| Process Technology | 0.45 um |
| Supply Voltage | 3.3 V / 5 V |
| Operating Temperature | -40C to +85C (Industrial) |
| Package | 84-LCC (J-Lead, PLCC-84, PLG84) |
| Mounting Type | Surface Mount |
| Programming Type | One-time programmable (OTP) |
| Lead Free | Yes (LEAD FREE per distributor data) |
| RoHS Status | [DATA_NEEDED: RoHS status] |
| Moisture Sensitivity Level | [DATA_NEEDED: MSL level] |
| Configuration Boot Time | None (instant-on, no configuration load) |
A42MX16-3PLG84I Pin Configuration
| Pin 1 | IO — User configurable I/O |
| Pin 7 | VDD — Core/IO supply (3.3V/5V system) |
| Pin 11 | GND — Ground |
| Pin 21 | IO/GCLK — User I/O or global clock input |
| Pin 22 | VPP — Programming voltage supply |
| Pin 42 | GND — Ground |
| Pin 63 | IO/GCLR — User I/O or global clear/reset |
| Pin 64 | VDD — Supply |
| Pin 84 | IO — User configurable I/O |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
A42MX16-3PLG84I is suitable for 6 applications: Legacy PLD and ASIC Replacement, Industrial Control and Automation, Telecommunications Line Cards, Medical Diagnostic Equipment, Aerospace and Defense Ground Systems, Test and Measurement Instrumentation.
Legacy PLD and ASIC Replacement
The MX family is positioned by Microchip as a reliable, single-chip ASIC alternative for consolidating legacy PLDs, GALs, and discontinued ASICs into one low-cost device. The A42MX16-3PLG84I provides 24K gates and 72 I/O with 5V-tolerant signaling, matching the electrical environment of 1990s-era boards. Its OTP programming means instant-on operation with no configuration memory to fail or be corrupted, and the 0.45um mature process guarantees long-term supply continuity that newer process nodes cannot match. Designers migrate original PLD equations into Libero SoC and re-close timing on the -3 speed grade.
Recommended
Industrial Control and Automation
Factory automation controllers, motor interface boards, and sensor aggregation modules benefit from the A42MX16-3PLG84I's -40C to +85C industrial temperature rating and 5V-compatible 72 I/O. The PLCC J-lead package tolerates the thermal cycling of industrial environments better than fine-pitch BGAs, and its 0.65mm-ish lead pitch allows hand rework on the production floor. Because MX devices are OTP, configuration is tamper-resistant in fielded equipment. Place the FPGA between 5V sensor banks and a 3.3V microcontroller bus, using its dual-voltage I/O to bridge both domains without level shifters.
Recommended
Telecommunications Line Cards
Legacy telecom and datacom line cards frequently used Actel MX FPGAs for framing, glue logic, and backplane interfacing, and the A42MX16-3PLG84I sustains those designs with 142/237 MHz toggling rates adequate for T1/E1-class and backplane timing. The 24K gate capacity absorbs address decode, interrupt control, and serial interface consolidation that previously consumed multiple PAL/GAL devices. The 84-PLCC socket-compatible footprint simplifies board-level maintenance in central-office equipment where card swaps must be fast. Instant-on OTP configuration means the card is active within microseconds of power application.
Recommended
Medical Diagnostic Equipment
Benchtop medical analyzers and imaging subsystems use the A42MX16-3PLG84I for deterministic, single-event-configured control logic where a corrupted SRAM configuration stream is unacceptable. The OTP fabric guarantees the same logic executes on every power-up, simplifying design verification for regulatory documentation. Its industrial temperature range covers typical clinical equipment environments, and 3.3V/5V I/O bridges modern ADC/DAC front ends to legacy 5V digital sections. Because medical product lifecycles span 10+ years, the MX family's long manufacturing history is a procurement advantage.
Recommended
Aerospace and Defense Ground Systems
Ground-based defense electronics, test sets, and radar support racks value the MX family's OTP design security and proven reliability; the related F-suffix (A42MX16-FPLG84) covers screened variants while the -3PLG84I serves benign-environment ground equipment. The instant-on, no-configuration-load behavior removes boot-time gaps in systems where logic must be live before system reset completes. The 24K gates implement bus arbitration, MIL-STD-style parallel interfaces, and built-in-test controllers. Designers should note the OTP constraint: use comprehensive simulation plus Libero timing closure before programming flight-adjacent hardware.
Recommended
Test and Measurement Instrumentation
Custom test fixtures, functional-board testers, and rack instrumentation use the A42MX16-3PLG84I as programmable glue between a PC host interface and device-under-test connectors. The 72 I/O and 142 MHz toggling handle pattern generation and capture at moderate speeds, while 5V-tolerant I/O directly drives TTL-level DUT boards without level translators. PLCC packages are socketable, allowing a single fixture PCB to accept different MX densities (A42MX16 to A42MX24) as fixture complexity grows. Reuse of one footprint across density grades shortens fixture respin cycles when test requirements expand.
Recommended
Recommended Products Summary
Engineering reference data for A42MX16-3PLG84I — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | A42MX16-3PLG84 | A42MX16-2PLG84I | A42MX24-3PLG84I |
|---|---|---|---|---|
| Brand | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology |
| Package | 84-PLCC (PLG84) | 84-PLCC - same | 84-PLCC - same | 84-PLCC - same |
| System Gates | 24000 | 24000 | 24000 | 36000 |
| Speed Grade | -3 | -3 | -2 | -3 |
| Temperature Range | -40C to +85C (I) | Commercial | -40C to +85C | -40C to +85C |
| Supply Voltage | 3.3 V / 5 V | 3.3 V / 5 V | 3.3 V / 5 V | 3.3 V / 5 V |
| Programming Type | One-time programmable | One-time programmable | One-time programmable | One-time programmable |
| User I/O | 72 | 72 | 72 | [DATA_NEEDED] |
| Relative Unit Price (tier 1) | ~$32.50 as of 2026-08-30 | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] |
Key Differentiators
- Fastest standard speed grade in the MX 24K-gate family (vs A42MX16-2PLG84I)
- Industrial temperature rating for fielded equipment (vs A42MX16-3PLG84)
- Lower cost with full timing margin for relaxed designs (vs A42MX16-1PLG84I)
Design Notes
Decouple every VDD pin of the 84-PLCC package with a 0.1uF ceramic capacitor placed within 5 mm of the pin, plus one 10uF bulk capacitor per supply rail. The MX 5.0V-tolerant architecture supports 3.3V/5V systems; keep VPP (programming supply) at its specified level only during programming and per datasheet guidance in operation. Estimate current with the Libero SoC power calculator since dynamic consumption scales with toggle rate toward the 142/237 MHz limits.
The 42MX family is one-time programmable (OTP). Unlike SRAM FPGAs, a functional bug after programming cannot be patched - the device is consumed. Complete RTL simulation, static timing closure at your actual operating corner, and (where feasible) program and validate an engineering-lot unit before committing a production build. Also confirm speed grade (-3 vs -1/-2) at ordering, since slower grades will fail timing closure on aggressive designs.
The PLCC-84 J-lead package is socket-compatible (e.g., PLCC sockets for field-replaceable designs) - use a quality socket if the design requires device replacement, since sockets add inductance on clock lines; keep the global clock (IO/GCLK pin) trace short and series-terminate if driving from an off-package oscillator. J-leads are also easier to rework than BGA, enabling hand repair in low-volume industrial builds.
With 5V-tolerant I/O at 72 pins, simultaneous switching output (SSO) noise on ground returns is the dominant integrity risk. Limit the number of I/O switching on the same bank per clock edge, distribute ground pins across the design, and verify ground bounce with the datasheet SSO guidelines. For 3.3V/5V mixed banks, honor the datasheet I/O bank voltage constraints during pin assignment in Libero.
Compliance Information
Distributor listings (PCB Electronics, Kynix) explicitly mark the part LEAD FREE. Formal RoHS/REACH certificates should be requested from Microchip.
