AD7663ASTZ - 16-Bit 250kSPS Bipolar PulSAR ADC | Analog Devices
料号： AD7663ASTZ ✓ 量产中| 数量 | 单价 | 小计 |
|---|---|---|
| 1 | $19.47 | $19.47 |
| 10 | $17.85 | $178.50 |
| 100 | $15.5 | $1,550.00 |
| 500 | $13.95 | $6,975.00 |
| 1,000 | $12.4 | $12,400.00 |
| 3,000 | $11.2 | $33,600.00 |
AD7663ASTZ 概述
A SAR ADC is a successive-approximation register analog-to-digital converter that uses a binary-search algorithm and a charge-redistribution DAC to convert an analog input to a digital code in one conversion cycle per bit. SAR ADCs combine low latency (no pipeline delay) with deterministic latency, moderate-to-high resolution (12-18 bits), and excellent DC accuracy, making them ideal for multiplexed data acquisition, industrial process control, and instrumentation front-ends where small analog signals must be captured precisely at moderate sampling rates.
Key specifications include 16-bit resolution with no missing codes, ±3 LSB (max) INL (0.0046% of full scale), 90 dB typical SNR at 100 kHz input, and -100 dB typical THD at 100 kHz. The analog supply range is 4.75 V to 5.25 V and the digital supply can be 3 V or 5 V. Throughput is 250 kSPS in parallel-word mode and 200 kSPS in serial mode. The bipolar input range is achieved with on-chip input scaling and a wide-input-range driver, eliminating the need for external signal conditioning in most applications.
The AD7663 uses the proprietary PulSAR core, a switched-capacitor charge-redistribution architecture that delivers low power dissipation (typically 35 mW at 250 kSPS) and excellent dynamic performance for AC and DC signals. On-chip calibration removes gain and offset errors, while the input span logic allows software selection of ±10 V, 0-5 V, or 0-10 V ranges without external resistor networks.
Typical applications include industrial process control and data acquisition, multichannel multiplexed PLC analog input modules, precision instrumentation, vibration and acoustic analysis, medical imaging front-ends, and spectrum analyzer IF digitizers. The wide input range and high DC accuracy suit 4-20 mA loop digitization after a sense resistor.
A key design consideration is the requirement for adequate bypass capacitance on both AVDD and DVDD rails (typically 10 µF tantalum plus 100 nF ceramic) and short, symmetric analog traces to the IN+ and IN- pins to preserve common-mode rejection. Designers should also configure the OB/2C pin, the input range selection, and the read mode (parallel/serial) before issuing conversion starts.
This page synthesizes real-time distributor pricing, parametric alternatives with the same 48-LQFP footprint, and practical design guidance drawn from the Analog Devices AD7663 datasheet, not duplicating the raw datasheet content.
直接替换替代料： AD7663ASTZ ——相同封装，引脚兼容。需要 PCB 改动的不同封装料号已排除。
本系列中的变体
可与以下型号直接替换的同系列型号： AD7663ASTZ （相同外形与封装尺寸） ——差异在于 Architecture, Package, Input Type, MSL Level, Operating Temperature Range.
快速对比工具——选择替代料号进行并排对比：
AD7663ASTZRL
✅ 直接替换📋 参考替代料（不在目录中）
AD7665ASTZ
✅ 直接替换📋 参考替代料（不在目录中）
AD7667AST
✅ 直接替换📋 参考替代料（不在目录中）
AD7663AST
✅ 直接替换📋 参考替代料（不在目录中）
AD7606C-16BSTZ
✅ 直接替换 ⚠️ 规格未核验✓ 有现货
$49.2188 / 个
查看数据手册 →AD7663ASTZ 最大额定值与电气特性
| 分辨率 | 16 bit |
| 采样率 | 250 kSPS |
| Architecture | SAR (PulSAR charge-redistribution) |
| Number of Input Channels | 1 |
| Input Type | Differential (true bipolar ±10 V, 0-5 V, 0-10 V software-selectable) |
| Analog Supply Voltage (AVDD) | 4.75 V to 5.25 V (5 V typical) |
| Digital Supply Voltage (DVDD) | 2.7 V to 5.25 V |
| INL（积分非线性） | ±3 LSB max (0.0046% of full scale) |
| SNR (Signal-to-Noise Ratio) | 90 dB typ @ 100 kHz input |
| THD (Total Harmonic Distortion) | -100 dB typ @ 100 kHz input |
| Data Interface | Parallel / Serial (software-selectable) |
| Power Dissipation | 35 mW typ @ 250 kSPS (5 V) |
| 工作温度范围 | -40 °C to +85 °C |
| 封装 | 48-pin LQFP (7x7 mm), ST suffix |
| 安装类型 | Surface Mount |
| MSL 等级 | 3 (168 hours floor life) |
| RoHS 状态 | Compliant (Pb-free ST suffix) |
| Throughput (Parallel Mode) | 250 kSPS |
| Throughput (Serial Mode) | 200 kSPS |
AD7663ASTZ 引脚配置
| 引脚 1 | DB15 — Parallel data output bit 15 (MSB) |
| 引脚 2 | DB14 — Parallel data output bit 14 |
| 引脚 3 | DB13 — Parallel data output bit 13 |
| 引脚 4 | DB12 — Parallel data output bit 12 |
| 引脚 5 | DB11 — Parallel data output bit 11 |
| 引脚 6 | DB10 — Parallel data output bit 10 |
| 引脚 7 | DB9 — Parallel data output bit 9 |
| 引脚 8 | DB8 — Parallel data output bit 8 |
| 引脚 9 | DB7 — Parallel data output bit 7 |
| 引脚 10 | DB6 — Parallel data output bit 6 |
| 引脚 11 | DB5 — Parallel data output bit 5 |
| 引脚 12 | DB4 — Parallel data output bit 4 |
| 引脚 13 | DB3 — Parallel data output bit 3 |
| 引脚 14 | DB2 — Parallel data output bit 2 |
| 引脚 15 | DB1 — Parallel data output bit 1 |
| 引脚 16 | DB0 — Parallel data output bit 0 (LSB) |
| 引脚 17 | OB/2C — Output byte / two's complement select |
| 引脚 18 | RANGE — Analog input range select (with software mode) |
| 引脚 19 | RESET — Reset input (active low) |
| 引脚 20 | RD — Read input (active low) |
| 引脚 21 | CS — Chip select (active low) |
| 引脚 22 | WR/IMPULSE — Write / conversion start |
| 引脚 23 | BUSY — Output: busy during conversion (active high) |
| 引脚 24 | DRDY — Output: data ready (active low) |
| 引脚 25 | DGND — Digital ground |
| 引脚 26 | DVDD — Digital supply (2.7 V to 5.25 V) |
| 引脚 27 | DVDD — Digital supply (2.7 V to 5.25 V) |
| 引脚 28 | CLKOUT — Serial clock output |
| 引脚 29 | CLKIN — Serial clock input |
| 引脚 30 | DOUT — Serial data output |
| 引脚 31 | DCEN — Daisy-chain enable |
| 引脚 32 | AGND — Analog ground |
| 引脚 33 | AGND — Analog ground |
| 引脚 34 | REF — Reference voltage (2.5 V typical) |
| 引脚 35 | REFGND — Reference ground |
| 引脚 36 | REF — Reference voltage (2.5 V typical, bypass) |
| 引脚 37 | AGND — Analog ground |
| 引脚 38 | IN- — Differential analog input negative |
| 引脚 39 | IN+ — Differential analog input positive |
| 引脚 40 | AGND — Analog ground |
| 引脚 41 | AVDD — Analog supply (4.75 V to 5.25 V) |
| 引脚 42 | AVDD — Analog supply (4.75 V to 5.25 V) |
| 引脚 43 | AGND — Analog ground |
| 引脚 44 | AVDD — Analog supply (4.75 V to 5.25 V) |
| 引脚 45 | AVDD — Analog supply (4.75 V to 5.25 V) |
| 引脚 46 | AGND — Analog ground |
| 引脚 47 | AGND — Analog ground |
| 引脚 48 | AVDD — Analog supply (4.75 V to 5.25 V) |
典型应用
AD7663ASTZ 适用于 6 应用s: Industrial Process Control & Data Acquisition, Multichannel Multiplexed PLC Input Modules, Precision Instrumentation and Test Equipment, Vibration and Acoustic Analysis, Medical Imaging Front-Ends, Spectrum Analyzer IF Digitization.
Industrial Process Control & Data Acquisition
The AD7663ASTZ delivers 16-bit no-missing-codes accuracy and ±10 V true bipolar input range, making it ideal for industrial PLC analog input modules. The on-chip input scaling eliminates external resistor dividers, simplifying the analog front-end for ±10 V, 0-5 V, and 0-10 V signals. At 250 kSPS, the PulSAR pipeline provides deterministic single-cycle latency for multiplexed 4-20 mA loop digitization after a sense resistor. Compared to delta-sigma ADCs, the SAR architecture adds no pipeline delay, enabling fast control-loop response. Per the AD7663 datasheet, the ±3 LSB max INL and 90 dB SNR at 100 kHz keep process-control error below 0.005% of full scale across the industrial temperature range.
推荐
Multichannel Multiplexed PLC Input Modules
The AD7663ASTZ's 250 kSPS throughput and parallel interface are well matched to multiplexed analog input modules where a single ADC serves many channels via an input MUX. The deterministic SAR pipeline latency (one conversion cycle per bit) eliminates the pipeline-delay uncertainty of delta-sigma ADCs, making channel-to-channel timing predictable for synchronized sampling across multiple analog inputs. The 48-LQFP (7x7 mm) footprint simplifies PCB layout for high-density multichannel designs. Per the AD7663 datasheet, the bipolar input range accepts ±10 V directly, eliminating external level-shift signal conditioning. With 35 mW typical dissipation, thermal management is straightforward even at 250 kSPS continuous conversion.
推荐
Precision Instrumentation and Test Equipment
The AD7663ASTZ's 16-bit no-missing-codes resolution and ±3 LSB INL make it well suited for benchtop multimeters, oscilloscope digitizers, and precision data loggers. The 90 dB SNR at 100 kHz input preserves signal fidelity for AC measurements, while the -100 dB THD keeps harmonic distortion below 0.001% for clean-spectrum analysis. The parallel interface enables fast readout into an FPGA or DSP at the full 250 kSPS throughput. Per the AD7663 datasheet, the on-chip calibration removes gain and offset errors on every conversion, eliminating the need for periodic user recalibration in most pipeline signal paths.
推荐
Vibration and Acoustic Analysis
The AD7663ASTZ's 250 kSPS sampling rate and 90 dB SNR at 100 kHz support vibration analysis, sonar modal and acoustic data acquisition up to 100 kHz bandwidth. The SAR pipeline architecture avoids delta-sigma pipeline delay, ensuring deterministic sample timing critical for FFT analysis and modal-vibration phase coherence. The bipolar ±10 V input range accepts signals directly from piezoelectric accelerometers via charge or IEPE amplifiers. Per the AD7663 datasheet, the 16-bit dynamic range (98 dB theoretical) keeps broadband noise floor below the signal of interest for vibration modal spectrum analysis at -100 dB THD.
推荐
Medical Imaging Front-Ends
The AD7663ASTZ's combination of 16-bit resolution, 250 kSPS throughput, and low-latency SAR pipeline suits medical imaging front-ends such as ultrasound beamformers and patient-monitoring analog front-ends. The deterministic latency ensures phase-aligned sampling across multiple channels, critical for beamforming and ECG/EEG multichannel alignment. The ±10 V bipolar input range accepts signals from ultrasound transducer preamps directly. Per the AD7663 datasheet, low 35 mW dissipation simplifies thermal design for portable patient-monitoring devices, and the 48-LQFP package enables compact multi-channel analog front-end PCBs.
推荐
Spectrum Analyzer IF Digitization
The AD7663ASTZ's 90 dB SNR at 100 kHz and -100 dB THD support IF digitization in low-frequency spectrum analyzers and dynamic signal analyzers up to 100 kHz bandwidth. The SAR pipeline delivers deterministic single-cycle latency, eliminating the pipeline-delay group-delay errors that corrupt FFT phase measurements in delta-sigma ADCs. The 250 kSPS sampling rate sets the Nyquist bandwidth at 125 kHz, covering audio and vibration spectrum-analysis bands. Per the AD7663 datasheet, the bipolar input accepts IF signals up to ±10 V directly, eliminating external attenuators in the IF pipeline.
推荐
推荐产品汇总
工程参考数据： AD7663ASTZ ——对比、设计指导和合规信息。
选型指南
与替代料对比
| 参数 | 本产品 | AD7663ASTZRL | AD7665ASTZ | AD7667AST | AD7606C-16BSTZ |
|---|---|---|---|---|---|
| Brand | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices |
| Package | 48-LQFP (7x7) | 48-LQFP (7x7) - same | 48-LQFP (7x7) - same | 48-LQFP (7x7) - same | 64-LQFP (10x10) - different |
| Resolution | 16 bit | 16 bit | 16 bit | 16 bit | 16 bit |
| Sampling Rate | 250 kSPS | 250 kSPS | 570 kSPS | 1 MSPS | 1 MSPS (8 channels simultaneous) |
| Input Channels | 1 | 1 | 1 | 1 | 8 |
| Input Range | ±10 V, 0-5 V, 0-10 V | ±10 V, 0-5 V, 0-10 V | ±10 V, 0-5 V, 0-10 V | ±10 V, 0-5 V, 0-10 V | ±10 V, ±5 V (per channel) |
| INL (max) | ±3 LSB | ±3 LSB | ±3 LSB | ±2.5 LSB | ±1 LSB |
| Architecture | PulSAR SAR | PulSAR SAR | PulSAR SAR | PulSAR SAR | PulSAR SAR (simultaneous sampling) |
| Data Interface | Parallel / Serial | Parallel / Serial | Parallel / Serial | Parallel / Serial | Parallel / Serial / SPI |
| 1ku List Price | $19.47 | $19.47 (same) | $24.50 | $32.10 | $42.00 |
关键差异点
- True bipolar ±10 V input range without external signal conditioning （对比 ADS8528 (Texas Instruments))
- PulSAR charge-redistribution pipeline with no pipeline delay （对比 AD7606C-16BSTZ (8-channel))
- Single 5 V analog supply
- Wide input range software selection （对比 ADS7253 (Texas Instruments))
设计说明
Estimated: Place a 10 µF tantalum plus 100 nF ceramic bypass on each AVDD pin (48-LQFP has 5 AVDD/AGND pin pairs) and on DVDD. Keep the trace length from each AVDD bypass cap to the package pin below 5 mm to minimize parasitic inductance, which would otherwise couple switching noise from the SAR charge-redistribution pipeline into the analog front-end. Per the AD7663 datasheet, inadequate supply decoupling can degrade SNR by 5-10 dB at full throughput.
Estimated: Route the analog input traces IN+ and IN- as a true differential microstrip with matched trace lengths (delta within 0.5 mm over 25 mm), 50 Ω characteristic impedance, and a continuous ground plane beneath. Keep digital outputs DB0-DB15, BUSY, and DRDY separated from the analog input pair by at least 5 mm or a ground guard trace. Per the AD7663 datasheet, mismatched IN+/IN- trace lengths degrade CMRR above 50 kHz input, so layout symmetry matters for the entire signal-conditioning pipeline.
Estimated: Do not exceed the analog input absolute maximum of 5.25 V or DVDD + 0.3 V, whichever is lower, on IN+ or IN-. The internal input divider is not overvoltage protected. Always use a clamp diode, sourcing clamp, or external buffer for high-energy inputs. Per the AD7663 datasheet, operating above abs-max damages the input pipeline ESD structures. Also note that the bipolar ±10 V range is software-selected; the RANGE pin logic must be configured correctly before initiating the conversion pipeline.
Estimated: Drive the REFGND pin with a clean analog ground separate from the digital ground returns. Place the 2.5 V reference bypass (10 µF tantalum + 100 nF ceramic) within 3 mm of the REF and REFGND pins. Reference noise directly couples into the SAR charge-redistribution pipeline accuracy, so a noisy reference degrades INL. Per the AD7663 datasheet, the internal reference settles to 16-bit accuracy within 5 ms after power-up - the conversion pipeline should not start until after this settling.
Estimated: Provide a continuous unbroken analog ground plane under the 48-LQFP footprint and stitch the AGND and DGND pins to this plane with multiple vias. Separate the digital ground plane and analog ground plane and join them at a single point near the AGND pin of the ADC to avoid ground-loop noise coupling into the SAR pipeline. Per the AD7663 datasheet, the ground-plane layout is the single most important factor in achieving the datasheet's 90 dB SNR at 100 kHz.
合规信息
RoHS compliant per AD7663 datasheet marking (ST suffix). Lead-free (Pb-free) reflow compatible. Halogen-free status not explicitly stated in provided data. Not AEC-Q100 qualified - the AD7663 family targets industrial instrumentation, not automotive applications.
