ADC1010S105HN/C1:5 - 10-bit 105 MSPS ADC, LVDS/CMOS | Renesas
料号： ADC1010S105HN/C1:5 ✓ 量产中| 数量 | 单价 | 小计 |
|---|---|---|
| 1 | $14.85 | $14.85 |
| 10 | $13.62 | $136.20 |
| 100 | $12.05 | $1,205.00 |
| 500 | $10.78 | $5,390.00 |
| 1,000 | $9.62 | $9,620.00 |
ADC1010S105HN/C1:5 概述
A pipelined ADC (Analog-to-Digital Converter) is a type of high-speed data converter that processes analog samples in a cascade of low-resolution flash stages, achieving sample rates from tens to hundreds of MSPS while maintaining low latency. Pipelined ADCs sit in the hierarchy: ADC -> data converter -> mixed-signal IC -> semiconductor. They are the workhorse of communications infrastructure, radar, medical imaging, and high-speed test equipment, where successive-approximation (SAR) ADCs cannot keep up with input bandwidth.
Key performance highlights of the ADC1010S105HN/C1:5 include 62 dBFS SNR, 86 dBc SFDR, a 1 Vp-p to 2 Vp-p flexible analog input range, and selectable offset binary, two's complement, or gray code output formats. A clock-input divided-by-2 mode relaxes clock-distribution jitter in board layouts, while the integrated DCS corrects for non-50% duty-cycle clocks. LVDS DDR output mode enables low-EMI, low-power data transfer to a downstream FPGA at high sample rates.
The device is built on a 0.13 µm CMOS mixed-signal process with on-chip reference and sample-and-hold, eliminating external reference components. SPI programmability allows the system designer to trade output format, LVDS termination strength, and power-down modes on the fly, supporting adaptive system configurations across operating states.
Typical applications include wireless base-station receive channels, radar and LiDAR signal processing, medical ultrasound front-ends, portable and benchtop oscilloscopes, spectrum analyzers, and high-speed data-acquisition cards. The wide input bandwidth also supports direct IF sampling in software-defined radio.
When designing with this part, allocate a continuous ground plane beneath the HVQFN-40 exposed pad to keep theta-JA low at full 105 MSPS, and route differential clock and analog inputs with controlled 100 ohm impedance. De-couple AVDD and DVDD rails separately to avoid digital switching noise coupling into the analog front end.
This page synthesizes distributor pricing, drop-in alternative MPNs, and practical design notes not found in the manufacturer datasheet, providing an at-a-glance reference for the ADC1010S105HN/C1:5.
直接替换替代料： ADC1010S105HN/C1:5 ——相同封装，引脚兼容。需要 PCB 改动的不同封装料号已排除。
本系列中的变体
可与以下型号直接替换的同系列型号： ADC1010S105HN/C1:5 （相同外形与封装尺寸） ——差异在于 Package, Architecture, Number of Channels, Input Type, RoHS Status.
快速对比工具——选择替代料号进行并排对比：
ADC1010S125HN/C1:5
✅ 直接替换✓ 有现货
$22.1 / 个
查看数据手册 →ADC1010S080HN/C1:5
✅ 直接替换✓ 有现货
$7.32 / 个
查看数据手册 →ADC1010S065HN/C1:5
✅ 直接替换✓ 有现货
$7.4 / 个
查看数据手册 →ADC1003S050TS/C1
✅ 直接替换 ⚠️ 规格未核验✓ 有现货
$7.4 / 个
查看数据手册 →ADC1003S030TS/C1
✅ 直接替换 ⚠️ 规格未核验✓ 有现货
$4.05 / 个
查看数据手册 →ADC1010S105HN/C1:5 最大额定值与电气特性
| 分辨率 | 10 bit |
| Sample Rate | 105 MSPS (max) |
| Number of Channels | 1 |
| Architecture | Pipelined |
| Input Bandwidth | 600 MHz |
| 输入电压范围 | 1 Vp-p to 2 Vp-p (flexible) |
| SNR | 62 dBFS |
| SFDR | 86 dBc |
| 电源电压 | 3.0 V (single) |
| Power Dissipation | 430 mW at 80 MSPS |
| Digital Output | CMOS or LVDS DDR (selectable) |
| Output Format | Offset binary, two's complement, or gray code |
| Configuration Interface | SPI (Serial Peripheral Interface) |
| Special Features | Duty cycle stabilizer (DCS), clock divide-by-2, OTR detection |
| 工作温度 | -40C to +85C (industrial) |
| 封装 | HVQFN-40 (SOT618-1, 6x6 mm, 0.85 mm height) |
| 安装类型 | Surface Mount |
| Screening Level | Industrial |
| RoHS 状态 | Compliant |
ADC1010S105HN/C1:5 引脚配置
| 引脚 1 | AVDD — Analog 3.0 V supply |
| 引脚 2 | VIN+ — Differential analog input (positive) |
| 引脚 3 | VIN- — Differential analog input (negative) |
| 引脚 4 | VCM — Common-mode voltage output |
| 引脚 5 | REFT — Top reference decoupling |
| 引脚 6 | REFB — Bottom reference decoupling |
| 引脚 7 | GND — Analog ground |
| 引脚 8 | CLK+ — Differential clock input (positive) |
| 引脚 9 | CLK- — Differential clock input (negative) |
| 引脚 10 | CLKDIV — Clock divide-by-2 select |
| 引脚 11 | DCS — Duty cycle stabilizer enable |
| 引脚 12 | SCLK — SPI serial clock |
| 引脚 13 | SDI — SPI serial data input |
| 引脚 14 | SDO — SPI serial data output |
| 引脚 15 | CSN — SPI chip select (active low) |
| 引脚 16 | PD — Power-down input |
| 引脚 17 | OTR — Out-of-range output |
| 引脚 18 | RESET — Digital reset |
| 引脚 19 | DVDD — Digital 3.0 V supply |
| 引脚 20 | GND — Digital ground |
| 引脚 21 | D0/D0+ — Data output bit 0 (CMOS or LVDS+) |
| 引脚 22 | D1/D0- — Data output bit 1 (CMOS or LVDS-) |
| 引脚 23 | D2/D1+ — Data output bit 2 (CMOS or LVDS+) |
| 引脚 24 | D3/D1- — Data output bit 3 (CMOS or LVDS-) |
| 引脚 25 | D4/D2+ — Data output bit 4 (CMOS or LVDS+) |
| 引脚 26 | D5/D2- — Data output bit 5 (CMOS or LVDS-) |
| 引脚 27 | D6/D3+ — Data output bit 6 (CMOS or LVDS+) |
| 引脚 28 | D7/D3- — Data output bit 7 (CMOS or LVDS-) |
| 引脚 29 | D8/D4+ — Data output bit 8 (CMOS or LVDS+) |
| 引脚 30 | D9/D4- — Data output bit 9 (CMOS or LVDS-) |
| 引脚 31 | DCLK+ — Data clock LVDS+ (DDR mode) |
| 引脚 32 | DCLK- — Data clock LVDS- (DDR mode) |
| 引脚 33 | OUTMODE — Output mode select (CMOS/LVDS) |
| 引脚 34 | FMT0 — Output format select bit 0 |
| 引脚 35 | FMT1 — Output format select bit 1 |
| 引脚 36 | NC — Not connected |
| 引脚 37 | NC — Not connected |
| 引脚 38 | GND — Ground |
| 引脚 39 | AVDD — Analog 3.0 V supply |
| 引脚 40 | GND — Exposed thermal pad (EPAD) - must be soldered to PCB ground |
典型应用
ADC1010S105HN/C1:5 适用于 6 应用s: Wireless Base-Station Receiver, Medical Ultrasound Front-End, Portable Oscilloscope and Data Acquisition, Software-Defined Radio (SDR) and Signal Intelligence, Radar and LiDAR Signal Processing, Industrial Imaging and Machine Vision.
Wireless Base-Station Receiver
The ADC1010S105HN/C1:5 directly samples intermediate-frequency (IF) signals in wireless base-station receive chains, replacing multi-stage downconversion with a single mixer-less path. Its 600 MHz input bandwidth supports IF frequencies up to approximately 200 MHz, while 62 dBFS SNR preserves EVM (Error Vector Magnitude) for LTE and 5G NR signals. The 105 MSPS sample rate comfortably digitizes 20 MHz LTE channels with room for guard bands, and LVDS DDR outputs minimize EMI on long backplane traces. Power dissipation of 430 mW at 80 MSPS is well within base-station thermal budgets.
推荐
Medical Ultrasound Front-End
The ADC1010S105HN/C1:5 digitizes broadband transducer echo signals in medical ultrasound imaging systems, where its 10-bit resolution and 105 MSPS throughput support the high-dynamic-range demands of harmonic imaging modes. The 1-2 Vp-p flexible input range allows direct coupling to time-gain-compensated (TGC) amplifier outputs without additional signal conditioning. The LVDS DDR output mode reduces cable emissions between the probe head and the cart-mounted processing unit, important for patient safety and EMC compliance. Industrial -40C to +85C rating supports portable cart and bedside equipment.
推荐
Portable Oscilloscope and Data Acquisition
The ADC1010S105HN/C1:5 serves as the front-end digitizer in benchtop and portable oscilloscopes, spectrum analyzers, and PC-based data-acquisition cards. The 600 MHz analog input bandwidth exceeds the 105 MSPS Nyquist limit, allowing undersampling of repetitive signals to extend effective bandwidth to several hundred MHz. The built-in duty-cycle stabilizer (DCS) corrects non-50% clock duty cycles that would otherwise create sample-time jitter and degrade SFDR, and the SPI configuration interface lets the host FPGA adapt output format on the fly.
推荐
Software-Defined Radio (SDR) and Signal Intelligence
The ADC1010S105HN/C1:5 is a popular direct-IF sampling ADC in software-defined radio platforms, where its 600 MHz input bandwidth allows capture of wide-spectrum segments without analog downconversion. With 62 dBFS SNR at 105 MSPS, it provides sufficient dynamic range for weak-signal detection in signal-intelligence and amateur-radio transceivers. The clock-input divide-by-2 mode relaxes FPGA clock-distribution requirements, and the LVDS DDR output reduces EMI in densely populated radio modules. The exposed-pad HVQFN-40 package simplifies thermal management in sealed enclosures.
推荐
Radar and LiDAR Signal Processing
In automotive and industrial radar systems, the ADC1010S105HN/C1:5 digitizes the IF output of the radar receiver mixer, supporting FMCW (Frequency-Modulated Continuous Wave) chirp analysis up to several hundred MHz of baseband. Its fast Out-of-Range (OTR) detection simplifies clutter-suppression logic in the downstream DSP, and 86 dBc SFDR preserves target-discrimination performance in dense multi-target scenarios. For LiDAR, the ADC can sample the output of avalanche photodiode (APD) receivers after transimpedance amplification, where 10-bit resolution is sufficient for time-of-flight peak detection.
推荐
Industrial Imaging and Machine Vision
The ADC1010S105HN/C1:5 digitizes high-speed line-scan camera outputs in industrial inspection systems, where pixel rates up to 105 MSPS support multi-megapixel-per-second throughput. The CMOS output mode interfaces directly to low-cost FPGAs and image processors, and the SPI-configurable output format (offset binary, two's complement, or gray code) simplifies downstream data alignment. Industrial temperature rating ensures reliable operation in factory-floor environments with elevated ambient temperatures and vibration. The LVDS DDR mode is preferred for cable runs exceeding 10 cm to preserve signal integrity.
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推荐产品汇总
工程参考数据： ADC1010S105HN/C1:5 ——对比、设计指导和合规信息。
选型指南
与替代料对比
| 参数 | 本产品 | ADC1010S125HN/C1:5 | ADC1010S080HN/C1:5 | ADC1010S065HN/C1:5 |
|---|---|---|---|---|
| Brand | Renesas Electronics | Renesas Electronics | Renesas Electronics | Renesas Electronics |
| Package | HVQFN-40 (SOT618-1, 6x6 mm) | HVQFN-40 (SOT618-1, 6x6 mm) - same | HVQFN-40 (SOT618-1, 6x6 mm) - same | HVQFN-40 (SOT618-1, 6x6 mm) - same |
| Sample Rate (max) | 105 MSPS | 125 MSPS (+19%) | 80 MSPS (-24%) | 65 MSPS (-38%) |
| Resolution | 10 bit | 10 bit | 10 bit | 10 bit |
| Number of Channels | 1 | 1 | 1 | 1 |
| Input Bandwidth | 600 MHz | 600 MHz | 600 MHz | 600 MHz |
| Digital Output | CMOS or LVDS DDR | CMOS or LVDS DDR | CMOS or LVDS DDR | CMOS or LVDS DDR |
| Supply Voltage | 3.0 V | 3.0 V | 3.0 V | 3.0 V |
| Operating Temperature | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C |
| Duty Cycle Stabilizer | Yes | Yes | Yes | Yes |
关键差异点
- Built-in Duty Cycle Stabilizer (DCS) tolerates non-50% clocks （对比 Generic 10-bit pipelined ADC without DCS)
- Single 3.0 V supply with CMOS or LVDS DDR output flexibility （对比 5 V supply ADCs (e.g., AD9430 family))
- 600 MHz input bandwidth enables direct IF sampling （对比 Narrower-bandwidth 10-bit ADCs (~200 MHz))
设计说明
The HVQFN-40 package relies on the central exposed pad (pin 40 EPAD) for heat dissipation. At 430 mW typical power and 1 W worst case at 105 MSPS, a continuous PCB ground plane directly beneath the EPAD is required to keep theta-JA low. Estimated: at 1 W dissipation and a typical 4-layer PCB ground-plane layout, junction temperature rise above ambient is approximately 30-40C, keeping the part within the -40C to +85C industrial rating when ambient stays below 50C. For sealed enclosures, add thermal vias to inner ground layers.
Route the differential clock (CLK+/CLK-) and analog input (VIN+/VIN-) pairs as 100 ohm differential transmission lines with controlled impedance. Keep trace lengths matched within 0.5 mm to preserve clock symmetry. Place AVDD and DVDD decoupling capacitors (10 uF bulk + 0.1 uF ceramic) as close to the supply pins as possible. Use separate analog and digital ground regions joined only at the EPAD to prevent digital switching noise from coupling into the analog front end, per the manufacturer datasheet layout guidance.
Do not exceed the 3.6 V absolute maximum on AVDD or DVDD; the part is not 5 V tolerant. Always enable the duty cycle stabilizer (DCS) when the input clock has a non-50% duty cycle, which is common after FPGA fanout buffers - without DCS, sample-time jitter degrades SFDR by 5-10 dB. Verify that the LVDS output mode is selected only when the downstream receiver is LVDS-compatible; driving LVDS outputs into a CMOS receiver will produce undefined logic levels. Use the SPI register map documented in the datasheet to reconfigure after a hardware reset.
For LVDS DDR output mode, route each data pair (D0+/D0- through D9+/D9-) and the DCLK pair as 100 ohm differential traces with length matching to within 0.25 mm of the clock. Keep LVDS output traces away from analog input traces and from the clock input pair to minimize crosstalk. Source-termination resistors are not required at the ADC end because the LVDS drivers are current-mode, but place a 100 ohm differential termination resistor at the receiver within 0.5 inch of the FPGA pins. Maintain a constant impedance reference plane beneath all LVDS traces.
合规信息
RoHS compliant per Renesas product page. Industrial temperature grade (-40C to +85C). Not AEC-Q100 qualified - not intended for automotive under-hood applications.
