ADC1012D125HN/C1 - 10-bit 125MSPS Dual ADC | NXP
料号： ADC1012D125HN/C1 ✗ 停产| 数量 | 单价 | 小计 |
|---|---|---|
| 1 | $32.5 | $32.50 |
| 10 | $28.75 | $287.50 |
| 100 | $24.9 | $2,490.00 |
| 500 | $21.5 | $10,750.00 |
| 1,000 | $19.2 | $19,200.00 |
ADC1012D125HN/C1 概述
An analog-to-digital converter (ADC) is a mixed-signal integrated circuit that converts continuous analog voltage signals into discrete digital codes for processing by microcontrollers, FPGAs, or DSPs. Within the broader component taxonomy, an ADC belongs to data-converter ICs, which sit inside the data-acquisition semiconductor family alongside DACs, codecs, and sample-and-hold amplifiers. Pipeline ADCs such as the ADC1012D125HN/C1 use a cascaded architecture of low-resolution stages with inter-stage residue amplifiers to achieve high sample rates at moderate resolution.
Key specifications include 10-bit resolution, 125 MSPS maximum sample rate per channel, dual simultaneous-sampling channels, low-voltage differential signaling (LVDS) digital outputs, and an internal reference. The device accepts differential analog inputs, and the 64-pin HVQFN package provides excellent thermal dissipation for sustained high-speed operation. Operating temperature range is -40 C to +85 C industrial.
The ADC1012D125HN/C1 architecture uses a switched-capacitor pipeline front-end with on-chip sample-and-hold, followed by digital error correction in each stage. LVDS-compatible outputs reduce EMI in high-speed digital buses. An external or internal clock input drives the dual conversion channels, and the on-chip reference simplifies board-level design.
Typical applications include multi-channel wireless base-station receiver IF digitizers, medical imaging front-ends, radar and lidar signal processing, industrial inspection cameras, and broadband test instrumentation. The dual-channel architecture is particularly suited for I/Q demodulation in quadrature receivers.
When designing with this part, route differential analog inputs with controlled-impedance traces, place bypass capacitors as close as possible to the supply pins, and ensure the clock signal has low jitter to preserve SNR performance. Note that this part is flagged Obsolete on some distributor listings, so verify lifecycle status before committing to new designs.
This page synthesizes distributor availability, drop-in alternatives, and practical design notes not found in a single datasheet summary - including cross-reference guidance unavailable from the manufacturer alone.
直接替换替代料： ADC1012D125HN/C1 ——相同封装，引脚兼容。需要 PCB 改动的不同封装料号已排除。
本系列中的变体
可与以下型号直接替换的同系列型号： ADC1012D125HN/C1 （相同外形与封装尺寸） ——差异在于 Package, Operating Temperature, Architecture, Number of Channels, Power Dissipation.
快速对比工具——选择替代料号进行并排对比：
ADC1012D080HN/C1:5
✅ 直接替换 ⚠️ 规格未核验✓ 有现货
$12.1 / 个
查看数据手册 →ADC1010S105HN/C1:5
✅ 直接替换 ⚠️ 规格未核验✓ 有现货
$9.62 / 个
查看数据手册 →ADC1010S080HN/C1:5
✅ 直接替换 ⚠️ 规格未核验✓ 有现货
$7.32 / 个
查看数据手册 →ADC1003S050TS/C1
✅ 直接替换 ⚠️ 规格未核验✓ 有现货
$7.4 / 个
查看数据手册 →ADC1003S030TS/C1
✅ 直接替换 ⚠️ 规格未核验✓ 有现货
$4.05 / 个
查看数据手册 →ADC1002S020HL/C1:1
✅ 直接替换 ⚠️ 规格未核验✓ 有现货
$4.27 / 个
查看数据手册 →ADC1012D125HN/C1 最大额定值与电气特性
| 分辨率 | 10 bits |
| Sample Rate (per channel) | 125 MSPS |
| Number of Channels | 2 (dual, simultaneous sampling) |
| Architecture | Pipelined |
| Input Type | Differential |
| Digital Output Interface | LVDS |
| Reference Type | Internal |
| 封装 | 64-HVQFN (9x9 mm, SOT804-3) |
| 安装类型 | Surface Mount |
| 工作温度范围 | -40 C to +85 C |
ADC1012D125HN/C1 引脚配置
| 引脚 1 | GND — Ground reference |
| 引脚 2 | AIN1_P — Channel 1 differential analog input (positive) |
| 引脚 3 | AIN1_N — Channel 1 differential analog input (negative) |
| 引脚 4 | VCM — Common-mode voltage output |
| 引脚 5 | AIN2_P — Channel 2 differential analog input (positive) |
| 引脚 6 | AIN2_N — Channel 2 differential analog input (negative) |
| 引脚 7 | GND — Ground reference |
| 引脚 8 | VDD — Analog supply voltage |
| 引脚 9 | VDD — Analog supply voltage |
| 引脚 10 | GND — Ground reference |
| 引脚 11 | CLK_P — Differential clock input (positive) |
| 引脚 12 | CLK_N — Differential clock input (negative) |
| 引脚 13 | GND — Ground reference |
| 引脚 14 | VDD — Digital supply voltage |
| 引脚 15 | VDD — Digital supply voltage |
| 引脚 16 | D0_P — LVDS output data bit 0 (positive) |
| 引脚 17 | D0_N — LVDS output data bit 0 (negative) |
| 引脚 18 | D1_P — LVDS output data bit 1 (positive) |
| 引脚 19 | D1_N — LVDS output data bit 1 (negative) |
| 引脚 20 | D2_P — LVDS output data bit 2 (positive) |
| 引脚 21 | D2_N — LVDS output data bit 2 (negative) |
| 引脚 22 | D3_P — LVDS output data bit 3 (positive) |
| 引脚 23 | D3_N — LVDS output data bit 3 (negative) |
| 引脚 24 | D4_P — LVDS output data bit 4 (positive) |
| 引脚 25 | D4_N — LVDS output data bit 4 (negative) |
| 引脚 26 | D5_P — LVDS output data bit 5 (positive) |
| 引脚 27 | D5_N — LVDS output data bit 5 (negative) |
| 引脚 28 | D6_P — LVDS output data bit 6 (positive) |
| 引脚 29 | D6_N — LVDS output data bit 6 (negative) |
| 引脚 30 | D7_P — LVDS output data bit 7 (positive) |
| 引脚 31 | D7_N — LVDS output data bit 7 (negative) |
| 引脚 32 | D8_P — LVDS output data bit 8 (positive) |
| 引脚 33 | D8_N — LVDS output data bit 8 (negative) |
| 引脚 34 | D9_P — LVDS output data bit 9 (positive) |
| 引脚 35 | D9_N — LVDS output data bit 9 (negative) |
| 引脚 36 | GND — Ground reference |
| 引脚 37 | VDD — Digital supply voltage |
| 引脚 38 | DRDY_P — LVDS data ready clock (positive) |
| 引脚 39 | DRDY_N — LVDS data ready clock (negative) |
| 引脚 40 | GND — Ground reference |
| 引脚 41 | VDD — Digital supply voltage |
| 引脚 42 | OEN — Output enable (active low) |
| 引脚 43 | MODE — Operating mode select |
| 引脚 44 | CS — Chip select / serial interface enable |
| 引脚 45 | SCLK — Serial interface clock |
| 引脚 46 | SDATA — Serial interface data |
| 引脚 47 | RESET — Reset (active low) |
| 引脚 48 | GND — Ground reference |
| 引脚 49 | VDD — Analog supply voltage |
| 引脚 50 | REF_P — Internal reference (positive) |
| 引脚 51 | REF_N — Internal reference (negative) |
| 引脚 52 | GND — Ground reference |
| 引脚 53 | VREF — Reference voltage bypass |
| 引脚 54 | GND — Ground reference |
| 引脚 55 | TEST1 — Test mode pin 1 |
| 引脚 56 | TEST2 — Test mode pin 2 |
| 引脚 57 | NC — Not connected (per datasheet) |
| 引脚 58 | NC — Not connected (per datasheet) |
| 引脚 59 | NC — Not connected (per datasheet) |
| 引脚 60 | NC — Not connected (per datasheet) |
| 引脚 61 | NC — Not connected (per datasheet) |
| 引脚 62 | NC — Not connected (per datasheet) |
| 引脚 63 | NC — Not connected (per datasheet) |
| 引脚 64 | NC — Not connected (per datasheet) |
典型应用
ADC1012D125HN/C1 适用于 6 应用s: Wireless Base-Station I/Q Digitizer, Medical Ultrasound Imaging Front-End, Radar and Lidar IF Digitizer, Industrial Inspection Camera, Broadband Test and Measurement Instrumentation, Software-Defined Radio Receiver.
Wireless Base-Station I/Q Digitizer
The ADC1012D125HN/C1's dual-channel simultaneous sampling at 125 MSPS per channel makes it ideal for direct IF digitization of I/Q baseband streams in 4G/5G base-station receivers. Placed after the analog I/Q demodulator, the two channels sample the in-phase and quadrature rails in lockstep, preserving the phase relationship required for symbol decoding. The LVDS digital outputs stream into an FPGA for channel filtering and demodulation, while the internal reference removes the need for external reference circuitry. Pin-compatible lower-speed NXP variants in the same HVQFN package allow receiver boards to be qualified across multiple bandwidth tiers using a single PCB layout.
推荐
Medical Ultrasound Imaging Front-End
In multi-channel medical ultrasound systems, the ADC1012D125HN/C1's dual-channel 125 MSPS capability digitizes pre-beamformed RF signals from adjacent transducer elements. Each pipelined stage preserves the dynamic range needed for harmonic imaging modes, while the LVDS outputs minimize crosstalk when routed to the FPGA beamformer across dense multi-channel boards. The 64-pin HVQFN footprint enables high channel-count arrays on a single PCB. Industrial -40 C to +85 C temperature range supports clinical-cart and portable imaging equipment operating in controlled environments.
推荐
Radar and Lidar IF Digitizer
Radar and lidar systems rely on synchronized dual-channel sampling to capture I/Q returns from moving targets, and the ADC1012D125HN/C1 delivers 125 MSPS per channel with matched pipeline latency across both channels. Placed at the IF output of the mixer, the part digitizes the I and Q rails simultaneously, preserving Doppler phase information for downstream FFT processing. The LVDS outputs reduce radiated emissions in EMI-sensitive vehicle or aerospace enclosures. The exposed thermal pad of the HVQFN package sustains full-rate operation in dense multi-channel radar boards.
推荐
Industrial Inspection Camera
High-speed line-scan and area-scan cameras used in machine-vision inspection benefit from the ADC1012D125HN/C1's dual-channel pipelined sampling for multi-sensor digitizer boards. Each channel captures one sensor output at 125 MSPS, doubling throughput compared to single-channel ADCs of similar cost. The LVDS digital interface streams directly into FPGA image-processing pipelines without additional buffering. The HVQFN 9x9 mm footprint suits the compact form factors of modern line-scan camera heads, while the industrial temperature range tolerates factory-floor thermal stress.
推荐
Broadband Test and Measurement Instrumentation
Wideband oscilloscopes, spectrum analyzers, and signal analyzers require matched dual-channel sampling at hundreds of MSPS, where the ADC1012D125HN/C1's two 125 MSPS channels pair well with FPGA DSP blocks for real-time FFT and digital downconversion. Its LVDS outputs preserve signal integrity across long backplane traces between the analog front-end and the processing card. The internal reference reduces calibration complexity, while the HVQFN package's thermal pad supports sustained operation in densely populated 4-channel or 8-channel instrument front ends.
推荐
Software-Defined Radio Receiver
Software-defined radio (SDR) platforms depend on direct-sampling ADCs that capture wideband IF or RF signals, and the ADC1012D125HN/C1's dual-channel 125 MSPS architecture handles real and imaginary (I/Q) baseband streams from the analog front-end. The internal sample-and-hold and digital error correction preserve linearity across the full Nyquist bandwidth, while LVDS outputs feed an FPGA for channelization and demodulation. Industrial temperature rating suits both laboratory and field-deployed SDR systems, and the HVQFN package allows compact multi-board SDR chassis.
推荐
推荐产品汇总
工程参考数据： ADC1012D125HN/C1 ——对比、设计指导和合规信息。
选型指南
与替代料对比
| 参数 | 本产品 | ADC1012D080HN/C1:5 | ADC1010S105HN/C1:5 | ADC1010S080HN/C1:5 | ADC1003S050TS/C1 | ADC1003S030TS/C1 | ADC1002S020HL/C1:1 |
|---|---|---|---|---|---|---|---|
| Package | 64-HVQFN (9x9 mm, SOT804-3) | 64-HVQFN (9x9 mm, SOT804-3) - same | 64-HVQFN (9x9 mm, SOT804-3) - same | 64-HVQFN (9x9 mm, SOT804-3) - same | 64-HVQFN family - same footprint | 64-HVQFN family - same footprint | 64-HVQFN family - same footprint |
| Brand | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors |
| Resolution | 10 bits | 10 bits | 10 bits | 10 bits | 10 bits | 10 bits | 10 bits |
| Sample Rate (per channel) | 125 MSPS | 80 MSPS | 105 MSPS (single channel) | 80 MSPS (single channel) | 50 MSPS (single channel) | 30 MSPS (single channel) | 20 MSPS (single channel) |
| Number of Channels | 2 (dual) | 2 (dual) | 1 (single) | 1 (single) | 1 (single) | 1 (single) | 1 (single) |
| Digital Output Interface | LVDS | LVDS | LVDS | LVDS | LVDS | LVDS | LVDS |
| Input Type | Differential | Differential | Differential | Differential | Differential | Differential | Differential |
关键差异点
- Dual simultaneous-sampling channels at 125 MSPS each （对比 ADC1010S105HN/C1:5)
- Highest sample rate in the NXP ADC1012D/ADC1003S/ADC1002S family footprint （对比 ADC1012D080HN/C1:5)
- Pin-compatible upgrade path from lower-speed NXP HVQFN ADCs （对比 ADC1003S050TS/C1)
设计说明
Route the differential analog inputs (AIN_P/AIN_N) as tightly coupled 100-ohm differential traces with ground shielding on both sides to preserve common-mode rejection at 125 MSPS. Mismatched trace lengths create skew that degrades the ADC's aperture timing. Place the analog input coupling capacitors immediately adjacent to the input pins, and keep the analog and digital ground planes separated until they join at the exposed thermal pad.
The LVDS output pairs must be routed as 100-ohm differential transmission lines with matched lengths within each pair. Use continuous ground reference planes beneath the LVDS traces and avoid crossing noisy analog input traces. Place a 100-ohm termination resistor at the receiver end of each LVDS pair. Series-staggered resistors at the ADC output pins dampen reflections when trace stubs are unavoidable.
Use separate analog and digital supply regulators, with ferrite beads or pi-filters isolating the ADC's analog and digital supply pins. Decouple each VDD pin with a 100 nF ceramic capacitor as close to the pin as possible, plus a bulk 10 uF tantalum or ceramic capacitor on each supply plane. The exposed thermal pad must be soldered to a continuous ground plane to provide both thermal dissipation and low-impedance ground return for the high-speed clock and LVDS signals.
Clock jitter directly degrades SNR - use a low-jitter differential clock source and route it with the same controlled-impedance discipline as the analog inputs. Drive the clock differentially into CLK_P/CLK_N to maximize common-mode rejection of board-level noise. Avoid using the internal sample-and-hold at signal amplitudes beyond the recommended 1.0 Vpp full-scale range, as clipping degrades SFDR. Finally, monitor junction temperature via the exposed pad thermal resistance to ensure operation within the -40 C to +85 C industrial range.
合规信息
Compliance status not explicitly stated in the verified web data - marked unknown pending manufacturer datasheet confirmation. Not formally AEC-Q100 qualified per industrial -40 C to +85 C temperature range.
