ADC11DL066CIVS/NOPB - Dual 11-Bit 66 MSPS ADC w/450MHz BW | TI
料号： ADC11DL066CIVS/NOPB ✗ 停产| 数量 | 单价 | 小计 |
|---|---|---|
| 1 | $18.5 | $18.50 |
| 10 | $16.75 | $167.50 |
| 100 | $14.2 | $1,420.00 |
| 500 | $12.1 | $6,050.00 |
| 1,000 | $10.6 | $10,600.00 |
ADC11DL066CIVS/NOPB 概述
An Analog-to-Digital Converter (ADC) is a data-conversion integrated circuit that transforms real-world analog signals into discrete digital codes for processing by DSPs, FPGAs, microcontrollers, or ASICs. ADCs sit in the signal chain between sensors/transducers and digital processors and are critical for defining system-level dynamic range, signal-to-noise ratio (SNR), and effective number of bits (ENOB). The ADC11DL066 belongs to the pipelined ADC sub-class, which uses multiple low-resolution flash stages and a digital correction block to deliver high sampling rates at moderate resolution with relatively low power consumption.
Key features include 66 MSPS sampling rate on each of two simultaneously sampled channels, 450 MHz analog input bandwidth for undersampling IF/RF signals, internal 1.0 V reference (with option for external reference), CMOS-compatible digital outputs, and a 3.3 V single-supply operation. The pipelined architecture delivers 7.5 effective bits typical at Nyquist and supports full-power input bandwidth beyond the second Nyquist zone.
The ADC11DL066 employs a fully differential pipelined architecture with per-stage MDAC and flash sub-ADC, internally trimmed gain and offset, and an on-chip bandgap reference. Its input stage uses a switched-capacitor sample-and-hold with a wideband input buffer, supporting both AC- and DC-coupled single-ended or differential drive networks. The internal reference can be bypassed to share an external precision reference across multiple converters for gain-matched multi-channel systems.
Typical applications include IF/baseband digitization in wireless infrastructure, medical ultrasound beamformers, portable test and measurement instrumentation, digital oscilloscopes and spectrum analyzers, dual-antenna diversity receivers, and CCD imaging front-ends. The dual simultaneous-sampling channels make it especially well-suited to I/Q demodulation and multichannel data acquisition.
When designing with this device, keep input traces short and use a differential drive network with 50 ohm terminations to preserve the 450 MHz input bandwidth. Provide low-impedance analog and digital supply planes, decouple close to each supply pin, and route LVCMOS outputs away from analog inputs to minimize digital coupling into the sample-and-hold. With sample rates beyond ~40 MSPS, a thermal estimate using the datasheet's typical power figure is recommended to size the PCB copper area; the 64-TQFP is a thermally enhanced package with an exposed-style pad path on the lead frame.
直接替换替代料： ADC11DL066CIVS/NOPB ——相同封装，引脚兼容。需要 PCB 改动的不同封装料号已排除。
快速对比工具——选择替代料号进行并排对比：
ADC12DL066CIVS/NOPB
✅ 直接替换📋 参考替代料（不在目录中）
ADC11DL066CIVSX/NOPB
✅ 直接替换 ⚠️ 规格未核验📋 参考替代料（不在目录中）
ADC10DL066CIVS/NOPB
✅ 直接替换 ⚠️ 规格未核验📋 参考替代料（不在目录中）
ADC1175-50CILQ/NOPB
✅ 直接替换📋 参考替代料（不在目录中）
ADC1175CIVQ/NOPB
✅ 直接替换 ⚠️ 规格未核验📋 参考替代料（不在目录中）
ADC11DL066CIVS/NOPB 最大额定值与电气特性
| Number of Bits | 11 |
| Number of Inputs | 2 (dual, simultaneous sampling) |
| Architecture | Pipelined |
| Sampling Rate (per channel) | 66 MSPS |
| Analog Input Bandwidth | 450 MHz |
| Data Interface | Parallel (CMOS) |
| Input Type | Differential, single-ended capable |
| Reference | Internal 1.0 V (external reference supported) |
| Number of Channels | 2 |
| Supply Voltage (Analog) | 3.3 V (typical) |
| Supply Voltage (Digital) | 3.3 V (typical) |
| 工作温度 | -40C to +85C (industrial) |
| 封装 / 外壳 | 64-TQFP (10x10 mm) |
| 安装类型 | Surface Mount |
| Packaging | Tray |
| RoHS 状态 | Compliant |
| Lead Free | Yes |
| Technology | CMOS, monolithic |
ADC11DL066CIVS/NOPB 引脚配置
| 引脚 1 | AGND — Analog ground |
| 引脚 2 | VA — Channel A analog input (+) |
| 引脚 3 | VA- — Channel A analog input (-) |
| 引脚 4 | AGND — Analog ground |
| 引脚 5 | AVDD — Analog 3.3V supply |
| 引脚 6 | VREF — Reference decoupling / external reference input |
| 引脚 7 | AGND — Analog ground |
| 引脚 8 | VB+ — Channel B analog input (+) |
| 引脚 9 | VB- — Channel B analog input (-) |
| 引脚 10 | AGND — Analog ground |
| 引脚 11 | CLK — Sample clock input |
| 引脚 12 | CLK- — Complementary sample clock (differential) |
| 引脚 13 | DGND — Digital ground |
| 引脚 14 | DVDD — Digital 3.3V supply |
| 引脚 15 | PD — Power-down control (active high) |
| 引脚 16 | DGND — Digital ground |
| 引脚 17 | DR_A0 — Channel A data output bit 0 (LSB) |
| 引脚 18 | DR_A1 — Channel A data output bit 1 |
| 引脚 19 | DR_A2 — Channel A data output bit 2 |
| 引脚 20 | DR_A3 — Channel A data output bit 3 |
| 引脚 21 | DR_A4 — Channel A data output bit 4 |
| 引脚 22 | DR_A5 — Channel A data output bit 5 |
| 引脚 23 | DR_A6 — Channel A data output bit 6 |
| 引脚 24 | DR_A7 — Channel A data output bit 7 |
| 引脚 25 | DR_A8 — Channel A data output bit 8 |
| 引脚 26 | DR_A9 — Channel A data output bit 9 |
| 引脚 27 | DR_A10 — Channel A data output bit 10 (MSB) |
| 引脚 28 | DGND — Digital ground |
| 引脚 29 | DR_B0 — Channel B data output bit 0 (LSB) |
| 引脚 30 | DR_B1 — Channel B data output bit 1 |
| 引脚 31 | DR_B2 — Channel B data output bit 2 |
| 引脚 32 | DR_B3 — Channel B data output bit 3 |
| 引脚 33 | DR_B4 — Channel B data output bit 4 |
| 引脚 34 | DR_B5 — Channel B data output bit 5 |
| 引脚 35 | DR_B6 — Channel B data output bit 6 |
| 引脚 36 | DR_B7 — Channel B data output bit 7 |
| 引脚 37 | DR_B8 — Channel B data output bit 8 |
| 引脚 38 | DR_B9 — Channel B data output bit 9 |
| 引脚 39 | DR_B10 — Channel B data output bit 10 (MSB) |
| 引脚 40 | DGND — Digital ground |
| 引脚 41 | NC — Not connected (per datasheet) |
| 引脚 42 | NC — Not connected (per datasheet) |
| 引脚 43 | FSRA — Frame/sync A (per datasheet) |
| 引脚 44 | FSRB — Frame/sync B (per datasheet) |
| 引脚 45 | DGND — Digital ground |
| 引脚 46 | DRDY_A — Data ready Channel A (per datasheet) |
| 引脚 47 | DRDY_B — Data ready Channel B (per datasheet) |
| 引脚 48 | DVDD — Digital 3.3V supply |
| 引脚 49 | NC — Not connected (per datasheet) |
| 引脚 50 | NC — Not connected (per datasheet) |
| 引脚 51 | AVDD — Analog 3.3V supply |
| 引脚 52 | AGND — Analog ground |
| 引脚 53 | VREF_OUT — Internal reference output (decouple externally) |
| 引脚 54 | AGND — Analog ground |
| 引脚 55 | VCM — Common-mode voltage output (per datasheet) |
| 引脚 56 | AVDD — Analog 3.3V supply |
| 引脚 57 | AGND — Analog ground |
| 引脚 58 | NC — Not connected (per datasheet) |
| 引脚 59 | NC — Not connected (per datasheet) |
| 引脚 60 | AVDD — Analog 3.3V supply |
| 引脚 61 | AGND — Analog ground |
| 引脚 62 | TEST — Test pin (per datasheet, leave floating or ground per app note) |
| 引脚 63 | DGND — Digital ground |
| 引脚 64 | DVDD — Digital 3.3V supply |
典型应用
ADC11DL066CIVS/NOPB 适用于 6 应用s: IF and Baseband Digitization in Wireless Receivers, Medical Ultrasound Beamforming Front-End, Portable Test and Measurement Instrumentation, Multi-Channel Data Acquisition Systems, Digital Oscilloscope and Spectrum Analyzer Front-End, CCD and Image Sensor Front-End Digitization.
IF and Baseband Digitization in Wireless Receivers
The ADC11DL066CIVS/NOPB's 450 MHz analog input bandwidth and 66 MSPS per channel support direct IF sampling at second- and third-Nyquist zones, eliminating an analog downconversion stage in receiver lineups. With 11-bit resolution and dual simultaneous channels, the device performs I/Q demodulation for SDR and diversity receivers while maintaining 7.5 effective bits typical at Nyquist. Designers typically place the part downstream of an anti-alias bandpass filter and feed it from a differential balun; unlike wider-input ADCs the 11-bit pipeline keeps per-channel power dissipation manageable in multi-channel antenna arrays.
推荐
Medical Ultrasound Beamforming Front-End
Dual simultaneous sampling at 66 MSPS with matched gain per channel makes the ADC11DL066CIVS/NOPB a strong fit for ultrasound beamformers, which require time-aligned channels across dozens of transducers. The integrated 1.0 V reference is shared across channels in array applications to keep gain drift correlated; the 450 MHz input bandwidth comfortably captures transducer harmonics up to the 6th or 7th band. The pipelined architecture delivers the throughput needed for real-time imaging while keeping per-channel power low enough to permit dense PCB placement in probe-head assemblies.
推荐
Portable Test and Measurement Instrumentation
Handheld oscilloscopes, spectrum analyzers, and signal analyzers benefit from the ADC11DL066CIVS/NOPB's 450 MHz input bandwidth and parallel CMOS output bus, which feeds an FPGA for DDC/FFT processing. Two channels enable simultaneous stimulus-and-response capture without external sample-mux switching, and the 3.3 V supply simplifies battery-isolated front-end design. Compared with higher-resolution pipeline ADCs, the 11-bit pipeline keeps the BOM cost low while preserving enough ENOB for sub-100 MHz measurements common in field-portable instruments.
推荐
Multi-Channel Data Acquisition Systems
The dual 66 MSPS channels of the ADC11DL066CIVS/NOPB map directly onto multi-channel DAS boards serving industrial vibration, sonar, and rotating-machine monitoring. The internal reference eliminates one external IC per channel, and the parallel LVCMOS output bus supports simultaneous read-out to an FPGA without serializer deserialization overhead. Industrial users should note the -40C to +85C qualification, well within typical control-room and outdoor-enclosure envelopes; the TQFP-64 footprint gives ~1.6 mm pad pitch for hand-rework-friendly prototypes.
推荐
Digital Oscilloscope and Spectrum Analyzer Front-End
The ADC11DL066CIVS/NOPB's 450 MHz analog input bandwidth directly supports 100 MHz+ real-time oscilloscope front-ends and HF spectrum analyzer IF chains. Two parallel channels let compact bench instruments support both scope and logic-like channels without doubling the BOM. Sub-Nyquist alias rejection is delivered by the board-level 5th-order Butterworth anti-alias filter driving the ADC's differential inputs; designers should budget ~3.5 ENOB for the front-end pipeline to retain usable dynamic range at full input bandwidth.
推荐
CCD and Image Sensor Front-End Digitization
The dual differential inputs of the ADC11DL066CIVS/NOPB accept correlated-double-sampled CCD outputs for digitizing image-sensor analog front-ends, where small signals near 1 V must be captured at clock-related sample instants. The 66 MSPS per-channel throughput suits VGA-grade sensor read rates and lower-resolution HD sensor streams. The internal 1.0 V reference is shared across channels to keep dark-current calibration baseline constant across the imaging array; PCB designers should pair the ADC with a quiet LDO such as the TPS7A4701 to drive AVDD and minimize spurious noise coupled into the sample-and-hold.
推荐
推荐产品汇总
工程参考数据： ADC11DL066CIVS/NOPB ——对比、设计指导和合规信息。
选型指南
与替代料对比
| 参数 | 本产品 | ADC12DL066CIVS/NOPB | ADC11DL066CIVSX/NOPB | ADC10DL066CIVS/NOPB | ADC1175-50CILQ/NOPB | ADC1175CIVQ/NOPB |
|---|---|---|---|---|---|---|
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| Package | 64-TQFP (10x10) | 64-TQFP (10x10) - same | 64-TQFP (10x10) - same | 64-TQFP (10x10) - same | 64-TQFP (10x10) - same | 64-TQFP (10x10) - same |
| Resolution | 11 bits | 12 bits (+1 bit) | 11 bits (same) | 10 bits (-1 bit) | 8 bits (-3 bits) | 8 bits (-3 bits) |
| Number of Channels | 2 | 2 (same) | 2 (same) | 2 (same) | 1 (half) | 1 (half) |
| Sampling Rate | 66 MSPS | 66 MSPS | 66 MSPS | 66 MSPS | 50 MSPS (-24%) | 20 MSPS (-70%) |
| Architecture | Pipelined | Pipelined | Pipelined | Pipelined | Pipelined (single-channel) | Pipelined (single-channel) |
| Lifecycle Status | NRND | Active | NRND (same die, T&R) | NRND | Obsolete / EOL | Obsolete / EOL |
关键差异点
- Dual simultaneous sampling at 66 MSPS in TQFP-64 （对比 ADC1175-50CILQ/NOPB)
- 11-bit pipelined with 450 MHz input bandwidth （对比 ADC1175CIVQ/NOPB)
- Pin-compatible 12-bit upgrade path （对比 ADC12DL066CIVS/NOPB)
设计说明
Place the ADC11DL066CIVS/NOPB within 5 mm of its anti-alias bandpass filter and balun, using a differential microstrip pair with 50 ohm characteristic impedance. Decouple each AVDD pin with a 100 nF X7R plus a 10 uF tantalum bulk cap within 2 mm of the pin, and place a small ferrite between AVDD and the LDO output to isolate switching noise from the sample-and-hold.
Route the 11-bit parallel CMOS data bus to the FPGA with matched-length traces (within +/- 2 mm) and a 30-50 ohm series damping resistor near the ADC outputs to suppress ringing. Keep the digital bus on the opposite PCB layer from the analog inputs, separated by a continuous ground plane so that digital-coupling return currents cannot leak into the analog front-end.
Estimated power dissipation at 66 MSPS full-rate, single 3.3 V supply, both channels active and 450 MHz input: plan for ~3.0 mW per MSPS per channel per the family datasheet. Size the PCB copper area under and around the TQFP-64 to keep junction rise under ~20 C; if a multi-board stack houses more than 4 ADCs, add a small aluminum heat-spreader or dedicated airflow path.
合规信息
/NOPB suffix confirms Pb-free, ROHS-compliant finish per TI ordering nomenclature. Not AEC-Q100 qualified; consult TI for automotive-grade 10/11/12-bit pipeline ADC equivalents.
