ADC1413D065HN-C1 - Dual 14-bit 65 Msps ADC | Renesas
料号： ADC1413D065HN-C1 ✓ 量产中| 数量 | 单价 | 小计 |
|---|---|---|
| 1 | $36.5 | $36.50 |
| 10 | $32.1 | $321.00 |
| 100 | $26.8 | $2,680.00 |
| 500 | $22.4 | $11,200.00 |
| 1,000 | $19.95 | $19,950.00 |
ADC1413D065HN-C1 概述
A pipelined ADC is a multi-stage converter that processes the analog input through successive lower-resolution sub-converter stages, each driving a residue amplifier for the next stage. Pipelined architectures deliver high conversion rates, low latency, and excellent linearity, making them the workhorse of high-speed data acquisition systems in communications infrastructure, digital oscilloscopes, and radar receivers. ADC1413D065HN-C1 specifically targets mid-speed, high-dynamic-range applications where the JESD204A serial interface simplifies multi-channel synchronization compared to LVDS parallel links.
The ADC1413D065HN-C1 series family covers 65, 80, 105, and 125 Msps speed grades from a single datasheet, so a designer can scale performance upward without changing pinout. Output error correction across the operating range guarantees no missing codes at 14 bits. An external reference input and the SPI control port allow per-channel gain and offset trimming for calibration in multi-board systems.
The device powers up through the JESD204A link, supporting deterministic latency across the serial interface. An integrated reference and sample-and-hold block reduce the external BOM, while the 56-pin 8x8 mm exposed-pad package keeps board area compact. Compared to 65 Msps parallel-output ADCs of similar resolution, the part typically reduces pin count by more than half and removes the FPGA timing-margin challenges of source-synchronous LVDS capture.
Typical applications include multi-antenna wireless base-station receivers, ultrasound beamforming front-ends, portable instrumentation digitizers, and software-defined-radio capture cards. The combination of 14-bit resolution, JESD204A serial output, and 65 Msps speed is well-matched to LTE and Wi-Fi observation paths.
When laying out the PCB, give priority to a continuous analog ground plane under the package, dedicated analog 3.3 V and digital 1.8 V supply planes, and matched-length PCB traces for the differential JESD204A lanes. Decoupling must use 100 nF ceramics at each supply pin and a 10 uF bulk capacitor within 25 mm of the exposed pad.
This page synthesizes Renesas and IDT distributor pricing, same-family drop-in speed-grade alternatives, and practical JESD204A layout notes not found on a typical distributor page.
直接替换替代料： ADC1413D065HN-C1 ——相同封装，引脚兼容。需要 PCB 改动的不同封装料号已排除。
本系列中的变体
可与以下型号直接替换的同系列型号： ADC1413D065HN-C1 （相同外形与封装尺寸） ——差异在于 Package, Input Type, Operating Temperature, Data Interface, Number of Inputs.
快速对比工具——选择替代料号进行并排对比：
ADC1413D080HN-C1
✅ 直接替换📋 参考替代料（不在目录中）
ADC1413D105HN-C1
✅ 直接替换✓ 有现货
$33.4 / 个
查看数据手册 →ADC1413D125HN-C1
✅ 直接替换📋 参考替代料（不在目录中）
ADC1410S105HN-C1
✅ 直接替换 ⚠️ 规格未核验✓ 有现货
$17.8 / 个
查看数据手册 →ADC1412D065HN-C1
✅ 直接替换✓ 有现货
$21.45 / 个
查看数据手册 →ADC1413D065HN-C1 最大额定值与电气特性
| 分辨率 | 14 bit |
| Number of Channels | 2 (dual) |
| Sample Rate | 65 Msps |
| Sample Rate (Family Range) | 65 / 80 / 105 / 125 Msps |
| Architecture | Pipelined |
| Output Interface | Serial JESD204A (2 lanes differential) |
| Configuration Interface | SPI (Serial Peripheral Interface) |
| Analog Supply Voltage | 3.3 V |
| Digital / Output-Driver Supply | 1.8 V |
| Missing Codes Guarantee | 0 (no missing codes over operating range) |
| Reference | Internal / external (per datasheet) |
| 封装 | HVQFN-56 / 56-VFQFPN (8x8 mm, 0.85 mm height, MO-220, SOT684-7) |
| 安装类型 | Surface Mount |
| 工作温度 | -40 C to +85 C (Industrial) |
| Screening Level | Industrial |
| Pin / Pad Count | 56 |
ADC1413D065HN-C1 引脚配置
| 引脚 1 | VA3P3 — Analog 3.3 V supply |
| 引脚 2 | GND — Analog ground |
| 引脚 3 | INP_A — Channel A positive analog input |
| 引脚 4 | INN_A — Channel A negative analog input |
| 引脚 5 | VCM_A — Channel A input common-mode voltage |
| 引脚 6 | GND — Analog ground |
| 引脚 7 | VA3P3 — Analog 3.3 V supply |
| 引脚 8 | GND — Analog ground |
| 引脚 9 | REFIO — Reference voltage I/O |
| 引脚 10 | REFTOP — Top reference decoupling |
| 引脚 11 | REFBOT — Bottom reference decoupling |
| 引脚 12 | GND — Analog ground |
| 引脚 13 | VA3P3 — Analog 3.3 V supply |
| 引脚 14 | INP_B — Channel B positive analog input |
| 引脚 15 | INN_B — Channel B negative analog input |
| 引脚 16 | VCM_B — Channel B input common-mode voltage |
| 引脚 17 | GND — Analog ground |
| 引脚 18 | VA3P3 — Analog 3.3 V supply |
| 引脚 19 | GND — Analog ground |
| 引脚 20 | VD1P8 — Digital 1.8 V supply |
| 引脚 21 | GND — Digital ground |
| 引脚 22 | VD1P8 — Digital 1.8 V supply |
| 引脚 23 | DOUT_P0 — JESD204A lane 0 positive output |
| 引脚 24 | DOUT_N0 — JESD204A lane 0 negative output |
| 引脚 25 | DOUT_P1 — JESD204A lane 1 positive output |
| 引脚 26 | DOUT_N1 — JESD204A lane 1 negative output |
| 引脚 27 | GND — Digital ground |
| 引脚 28 | VD1P8 — Digital 1.8 V supply |
| 引脚 29 | SYNC_P — JESD204A SYNC positive input |
| 引脚 30 | SYNC_N — JESD204A SYNC negative input |
| 引脚 31 | GND — Digital ground |
| 引脚 32 | CLK_P — Sampling clock positive input |
| 引脚 33 | CLK_N — Sampling clock negative input |
| 引脚 34 | GND — Digital ground |
| 引脚 35 | VD1P8 — Digital 1.8 V supply |
| 引脚 36 | CSB — SPI chip select (active low) |
| 引脚 37 | SCLK — SPI serial clock |
| 引脚 38 | SDIO — SPI serial data I/O |
| 引脚 39 | SDO — SPI serial data output |
| 引脚 40 | RESETB — Hardware reset (active low) |
| 引脚 41 | GND — Digital ground |
| 引脚 42 | VD1P8 — Digital 1.8 V supply |
| 引脚 43 | TEST1 — Test mode pin 1 (factory use) |
| 引脚 44 | TEST2 — Test mode pin 2 (factory use) |
| 引脚 45 | TEST3 — Test mode pin 3 (factory use) |
| 引脚 46 | TEST4 — Test mode pin 4 (factory use) |
| 引脚 47 | GND — Analog ground |
| 引脚 48 | VA3P3 — Analog 3.3 V supply |
| 引脚 49 | GND — Analog ground |
| 引脚 50 | VA3P3 — Analog 3.3 V supply |
| 引脚 51 | NC — Not connected (per datasheet) |
| 引脚 52 | NC — Not connected (per datasheet) |
| 引脚 53 | GND — Analog ground |
| 引脚 54 | VA3P3 — Analog 3.3 V supply |
| 引脚 55 | NC — Not connected (per datasheet) |
| 引脚 56 | VA3P3 — Analog 3.3 V supply |
| 引脚 57 | EPAD — Exposed thermal pad, must be soldered to analog ground |
典型应用
ADC1413D065HN-C1 适用于 6 应用s: Wireless Base-Station Receiver, Medical Ultrasound Beamformer, Software-Defined Radio Capture Card, Portable Digital Oscilloscope, Industrial Data Acquisition Module, Radar L-Band Receiver.
Wireless Base-Station Receiver
The ADC1413D065HN-C1 fits multi-antenna LTE and Wi-Fi observation receivers that digitize two parallel RF paths at baseband. Its 14-bit resolution (84 dB SNR) and 65 Msps per channel easily handle 20 MHz LTE signals while leaving 30 dB of margin for adjacent-channel interferers. JESD204A serial output with deterministic latency aligns both channels across the FPGA, simplifying MIMO calibration. Powered from 3.3 V analog and 1.8 V digital rails, the part integrates directly into typical remote-radio-head designs.
推荐
Medical Ultrasound Beamformer
Ultrasound front-ends digitize returning echoes from up to 128 transducer elements at 30-65 Msps and route them through digital beamforming logic. The ADC1413D065HN-C1's two-channel architecture doubles channel density per package, while the JESD204A interface streams the data directly to an FPGA-based beamformer over a small number of board traces. The 14-bit dynamic range satisfies clinical imaging's 60 dB requirement, and the industrial -40 C to +85 C rating tolerates chassis-internal temperatures in cart-based systems.
推荐
Software-Defined Radio Capture Card
A wideband SDR captures RF signals from HF through microwave bands by sampling intermediate-frequency (IF) signals at tens of Msps. The ADC1413D065HN-C1 at 65 Msps captures up to 30 MHz of instantaneous bandwidth per channel, and its two channels support diversity or dual-antenna feeds in a single chip. JESD204A streams the digitized I/Q into a host FPGA, which performs channelization in DSP. The pipelined core guarantees zero missing codes, critical for digital demodulation accuracy and bit-error-rate benchmarks.
推荐
Portable Digital Oscilloscope
Modern handheld oscilloscopes digitize two or four analog input channels at 50-200 Msps to drive their LCD graphics. The ADC1413D065HN-C1's dual 14-bit / 65 Msps profile suits a 2-channel scope with 30 MHz of analog bandwidth, well within the part's Nyquist limit. The JESD204A interface streams data into a low-cost FPGA that runs the trigger and measurement engine. The 56-VFQFPN 8x8 mm package fits the tight board layouts of handheld instruments.
推荐
Industrial Data Acquisition Module
Multi-channel industrial DAQ modules digitize vibration, strain-gage, or power-quality signals at sample rates from 10-65 kS/s to several Msps. The ADC1413D065HN-C1 can oversample slower transducer signals to extract 16-bit effective resolution through averaging, while the second channel doubles device density. SPI configuration allows per-channel gain and offset calibration in factory test, important for accuracy across temperature. The industrial temperature grade supports deployment in factory-floor enclosures.
推荐
Radar L-Band Receiver
L-band surveillance and weather radars digitize IF stages at 30-65 Msps with 12-14 bits of dynamic range to detect small targets inside large clutter returns. The ADC1413D065HN-C1's dual channels ease dual-polarization radar design, while JESD204A links multiple boards together deterministically, which is essential for phased-array coherence. The 3.3 V analog supply simplifies LNA bias network design and reduces overall receiver power compared to 5 V legacy ADCs.
推荐
推荐产品汇总
工程参考数据： ADC1413D065HN-C1 ——对比、设计指导和合规信息。
选型指南
与替代料对比
| 参数 | 本产品 | ADC1413D080HN-C1 | ADC1413D105HN-C1 | ADC1413D125HN-C1 | ADC1412D065HN-C1 | ADC1410S105HN-C1 |
|---|---|---|---|---|---|---|
| Brand | Renesas Electronics | Renesas Electronics | Renesas Electronics | Renesas Electronics | Renesas Electronics | Renesas Electronics |
| Package | 56-VFQFPN (8x8 mm, HVQFN-56) | 56-VFQFPN (8x8 mm) - same | 56-VFQFPN (8x8 mm) - same | 56-VFQFPN (8x8 mm) - same | 56-VFQFPN (8x8 mm) - same | 56-VFQFPN (8x8 mm) - same |
| Resolution | 14 bit | 14 bit | 14 bit | 14 bit | 12 bit | 14 bit |
| Sample Rate | 65 Msps | 80 Msps | 105 Msps | 125 Msps | 65 Msps | 105 Msps |
| Number of Channels | 2 (dual) | 2 (dual) | 2 (dual) | 2 (dual) | 2 (dual) | 1 (single) |
| Output Interface | JESD204A (serial) | JESD204A (serial) | JESD204A (serial) | JESD204A (serial) | JESD204A (serial) | JESD204A (serial) |
| Analog Supply | 3.3 V | 3.3 V | 3.3 V | 3.3 V | 3.3 V | 3.3 V |
| Digital Supply | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 1.8 V |
| Operating Temperature | -40 C to +85 C (Industrial) | -40 C to +85 C (Industrial) | -40 C to +85 C (Industrial) | -40 C to +85 C (Industrial) | -40 C to +85 C (Industrial) | -40 C to +85 C (Industrial) |
关键差异点
- JESD204A serial interface in a 56-pin 8x8 mm package （对比 ADS62P23 (parallel LVDS))
- Dual-channel 14-bit 65 Msps in a single chip （对比 ADC1410S105HN-C1 (single channel))
- Industrial -40 C to +85 C screening at 14 bits （对比 ADC1413D065HN/C1:5 tape-and-reel variant)
设计说明
Lay out a continuous analog ground plane directly under the 56-VFQFPN exposed pad, and stitch that pad to the analog ground with at least 8 thermal vias. Place 100 nF X7R 0402 ceramic bypass capacitors within 2 mm of every VA3P3 and VD1P8 supply pin, and add a shared 10 uF tantalum or ceramic bulk capacitor within 25 mm of the package. Keep the analog 3.3 V and digital 1.8 V planes physically separated to avoid digital switching noise coupling into the analog front end.
The JESD204A serial output lanes (DOUT_P0/N0, DOUT_P1/N1, SYNC_P/N) and the sampling clock (CLK_P/N) must be routed as 100 ohm differential pairs with length matching to within 0.5 mm within each pair and to within 5 mm between lanes. Use an AC-coupling capacitor of 10 nF in series with each differential driver output if the FPGA inputs do not tolerate the 1.8 V CML common-mode voltage directly.
Supply the analog 3.3 V rail from a low-noise LDO (such as a TPS7A47 or equivalent) rather than from a switching converter directly, because ADC1413D065HN-C1 PSRR at high input frequencies is limited. Recommended: Estimated, given 65 Msps, 3.3 V analog and 1.8 V digital rails, the ADC draws roughly 150-200 mW per channel; a 500 mA LDO headroom ensures startup transients do not collapse the rail.
合规信息
Operating temperature range -40 C to +85 C (industrial) confirmed by Renesas product page and distributor listings. RoHS, REACH, lead-free and halogen-free status not specified in the provided verified web data and should be confirmed against the manufacturer datasheet compliance statement.
