ADC1613D080HN-C1 - Dual 16-Bit 80MSPS ADC w/ JESD204A | Renesas
料号： ADC1613D080HN-C1 ✓ 量产中| 数量 | 单价 | 小计 |
|---|---|---|
| 1 | $47.5 | $47.50 |
| 10 | $42.75 | $427.50 |
| 100 | $38.1 | $3,810.00 |
| 500 | $34.2 | $17,100.00 |
| 1,000 | $30.95 | $30,950.00 |
ADC1613D080HN-C1 概述
An ADC (analog-to-digital converter) is a data-acquisition mixed-signal IC that samples a continuous analog waveform on each clock edge and quantises the instantaneous amplitude into a parallel or serial binary codeword; the dual-channel variant integrates two matched ADC cores clocked from a shared input, which is essential for I/Q demodulation, multi-antenna wireless receivers, and time-interleaved instrumentation. Pipeline ADCs like the ADC1613D080HN-C1 favour high sample rates and low per-channel power by distributing the conversion across many low-resolution stages, each driving a digital correction block.
Key features include dual 16-bit resolution, 80 MSPS maximum sample rate, a JESD204A serialiser that simplifies board routing by replacing wide LVDS buses with a low-pin-count high-speed serial link, integrated input buffers, and an exposed thermal pad that pulls heat directly from the die into the PCB copper pour. The 80 MSPS grade is typically the lowest power member of the family and is therefore favoured in compact multi-channel receivers.
The architecture uses a multi-stage switched-capacitor pipeline with proprietary error correction, an on-chip input termination network, and a JESD204A link layer that delivers deterministic latency and 8B/10B-encoded frames. This combination is engineered for cellular base-station observation receivers, multi-antenna test equipment, and phased-array radar digitisation where channel-to-channel matching and serialiser data integrity matter.
Typical applications include multi-carrier wireless base-station receiver cards, software-defined radio (SDR) front-ends, medical imaging ultrasound beamformers, and high-channel-count industrial data-acquisition backplanes. The dual channel pairing also suits direct-conversion I/Q sampling in zero-IF receivers.
When designing with this converter, allocate at least four PCB layers around the HVQFN exposed pad and stitch the thermal pad with a 4 x 4 grid of thermal vias to inner ground/plane layers; the JESD204A link also demands careful length matching of the CML serial pair and decoupling of the 1.9 V and 3.3 V supplies within 5 mm of the package.
This page synthesises distributor pricing, drop-in alternatives across the ADC1613D speed-grade family, and practical PCB layout guidance beyond the manufacturer datasheet summary.
直接替换替代料： ADC1613D080HN-C1 ——相同封装，引脚兼容。需要 PCB 改动的不同封装料号已排除。
本系列中的变体
可与以下型号直接替换的同系列型号： ADC1613D080HN-C1 （相同外形与封装尺寸） ——差异在于 Package, Output Interface, Number of Channels, Operating Temperature, Resolution.
快速对比工具——选择替代料号进行并排对比：
ADC1613D065HN-C1
✅ 直接替换📋 参考替代料（不在目录中）
ADC1613D105HN-C1
✅ 直接替换✓ 有现货
$19.4 / 个
查看数据手册 →ADC1613D125HN-C1
✅ 直接替换✓ 有现货
$24.95 / 个
查看数据手册 →ADC1613D080HN/C1:5
✅ 直接替换📋 参考替代料（不在目录中）
ADC1012D080HN/C1:5
✅ 直接替换✓ 有现货
$12.1 / 个
查看数据手册 →ADC1112D125HN-C18
✅ 直接替换✓ 有现货
$9.48 / 个
查看数据手册 →ADC1613D080HN-C1 最大额定值与电气特性
| 分辨率 | 16 bit |
| Number of Channels | 2 (dual) |
| Architecture | Pipelined |
| Sample Rate (max) | 80 MSPS |
| Sample Rate Family | 65 / 80 / 105 / 125 MSPS grades |
| Output Interface | JESD204A (serial) |
| 封装 | 56-VFQFN exposed pad (HVQFN-56, MO-220 / SOT684-7) |
| Package Body Size | 8 mm x 8 mm |
| Package Height | 0.85 mm |
| 引脚数量 | 56 |
| Screening Level | Industrial |
| 工作温度 | -40 C to +85 C |
| 安装类型 | Surface Mount |
| Manufacturer | Renesas Electronics (formerly IDT) |
ADC1613D080HN-C1 引脚配置
| 引脚 1 | GND — Ground (analog/digital common) |
| 引脚 2 | VA1P2 — 1.2 V analog supply, channel 1 |
| 引脚 3 | VIN1A — Analog input, channel 1 (positive) |
| 引脚 4 | VIN1B — Analog input, channel 1 (negative / complement) |
| 引脚 5 | VCM1 — Common-mode voltage reference, channel 1 |
| 引脚 6 | CLKINP — Differential clock input (positive) |
| 引脚 7 | CLKINN — Differential clock input (negative) |
| 引脚 8 | VA3P3 — 3.3 V analog supply |
| 引脚 9 | GND — Ground |
| 引脚 10 | VA1P2 — 1.2 V analog supply |
| 引脚 11 | VCM2 — Common-mode voltage reference, channel 2 |
| 引脚 12 | VIN2B — Analog input, channel 2 (negative / complement) |
| 引脚 13 | VIN2A — Analog input, channel 2 (positive) |
| 引脚 14 | VA1P2 — 1.2 V analog supply, channel 2 |
| 引脚 15 | GND — Ground |
| 引脚 16 | VA1P2 — 1.2 V digital supply |
| 引脚 17 | VD1P2 — 1.2 V digital core supply |
| 引脚 18 | GND — Ground |
| 引脚 19 | SDO — SPI serial data output for register access |
| 引脚 20 | SDI — SPI serial data input for register access |
| 引脚 21 | SCLK — SPI serial clock |
| 引脚 22 | CSN — SPI chip select (active low) |
| 引脚 23 | RESETN — Hardware reset (active low) |
| 引脚 24 | PDN — Power-down (active high) |
| 引脚 25 | GND — Ground |
| 引脚 26 | VD3P3 — 3.3 V digital I/O supply |
| 引脚 27 | SYSREF — JESD204A system reference signal |
| 引脚 28 | SYNCBN — JESD204A sync request (active low) |
| 引脚 29 | GND — Ground |
| 引脚 30 | DOUTP — JESD204A CML serial data output (positive) |
| 引脚 31 | DOUTN — JESD204A CML serial data output (negative) |
| 引脚 32 | GND — Ground |
| 引脚 33 | NC — Not connected (per datasheet) |
| 引脚 34 | NC — Not connected (per datasheet) |
| 引脚 35 | GND — Ground |
| 引脚 36 | NC — Not connected (per datasheet) |
| 引脚 37 | NC — Not connected (per datasheet) |
| 引脚 38 | VA1P2 — 1.2 V analog supply |
| 引脚 39 | VA1P2 — 1.2 V analog supply |
| 引脚 40 | GND — Ground |
| 引脚 41 | VA1P2 — 1.2 V analog supply |
| 引脚 42 | NC — Not connected (per datasheet) |
| 引脚 43 | NC — Not connected (per datasheet) |
| 引脚 44 | NC — Not connected (per datasheet) |
| 引脚 45 | NC — Not connected (per datasheet) |
| 引脚 46 | VD3P3 — 3.3 V digital I/O supply |
| 引脚 47 | GND — Ground |
| 引脚 48 | VD1P2 — 1.2 V digital core supply |
| 引脚 49 | GND — Ground |
| 引脚 50 | VA3P3 — 3.3 V analog supply |
| 引脚 51 | NC — Not connected (per datasheet) |
| 引脚 52 | NC — Not connected (per datasheet) |
| 引脚 53 | VA1P2 — 1.2 V analog supply |
| 引脚 54 | GND — Ground |
| 引脚 55 | NC — Not connected (per datasheet) |
| 引脚 56 | NC — Not connected (per datasheet) |
典型应用
ADC1613D080HN-C1 适用于 6 应用s: Wireless Base-Station Receiver Cards, Software-Defined Radio (SDR) Front-Ends, Medical Imaging Ultrasound Beamformers, Phased-Array Radar Digitisation, High-Channel-Count Industrial Data Acquisition, Direct-Conversion Zero-IF Receivers.
Wireless Base-Station Receiver Cards
The ADC1613D080HN-C1's dual 16-bit channels and 80 MSPS throughput make it well suited to multi-carrier cellular base-station observation receivers where two antenna streams must be digitised simultaneously. The JESD204A serialiser consolidates the data lanes into a single high-speed CML pair, simplifying PCB routing on densely populated receiver cards. Compared with two parallel-LVDS ADCs, the JESD204A interface eliminates wide bus matching and slashes FPGA pin count, while 80 MSPS comfortably handles several LTE carriers of baseband bandwidth per channel.
推荐
Software-Defined Radio (SDR) Front-Ends
Software-defined radio platforms benefit from the ADC1613D080HN-C1 because the 80 MSPS sample rate covers most narrowband and many wideband waveforms up to roughly 30 MHz of alias-protected bandwidth per Nyquist zone. The dual channel pairing supports direct-conversion I/Q sampling without an external analog quadrature splitter, eliminating I/Q amplitude and phase mismatch that degrades image rejection. The JESD204A interface streams the I/Q data directly into the FPGA's JESD204A IP core, removing LVDS bus skeW issues that plague wide parallel interfaces in SDR hardware.
推荐
Medical Imaging Ultrasound Beamformers
In multi-channel ultrasound beamformer front-ends, the ADC1613D080HN-C1 serves as a per-channel digitiser with enough speed (80 MSPS) to satisfy 2x oversampling of 30 MHz piezo transducer bandwidth while keeping noise and power low per channel. The dual channels can digitise two adjacent transducer elements with sample-aligned clocks, simplifying the FPGA's beamforming math. Industrial -40 C to +85 C operation also supports portable cart-based ultrasound systems used outside clinical environments.
推荐
Phased-Array Radar Digitisation
Phased-array radar modules need many tightly synchronised ADC channels, and the ADC1613D080HN-C1 fits as a two-element digitiser block with the JESD204A deterministic latency that radar beam steering requires. 80 MSPS comfortably digitises S-band baseband radar returns after analog down-conversion, and the HVQFN-56 exposed-pad package allows dense tiling of many converter ICs behind each antenna sub-array. Multi-channel sample coherence is maintained because all ADCs in the array can share the same device clock and frame clock.
推荐
High-Channel-Count Industrial Data Acquisition
Industrial data-acquisition backplanes digitising vibration, acoustic emission, or power-quality signals can deploy the ADC1613D080HN-C1 as a per-slot dual-channel front end. The 80 MSPS throughput oversamples most sensor bandwidths sufficiently for anti-aliasing, while the industrial -40 C to +85 C rating suits factory-floor enclosures. JESD204A serialisation concentrates the data onto a single backplane serialiser, allowing more ADC channels per slot than legacy parallel-LVDS designs could achieve.
推荐
Direct-Conversion Zero-IF Receivers
Zero-IF receivers downconvert RF signals directly to baseband I and Q streams, and the ADC1613D080HN-C1 digitises both I and Q channels simultaneously using its dual 16-bit cores. 80 MSPS oversamples typical 20 MHz-wide zero-IF baseband signals by 2x, easing analog filter roll-off requirements. The JESD204A serial output streams the I/Q samples deterministically into the demodulator FPGA, preserving the channel-matched timing essential for accurate I/Q demodulation.
推荐
推荐产品汇总
工程参考数据： ADC1613D080HN-C1 ——对比、设计指导和合规信息。
选型指南
与替代料对比
| 参数 | 本产品 | ADC1613D065HN-C1 | ADC1613D105HN-C1 | ADC1613D125HN-C1 | ADC1613D080HN/C1:5 | ADC1012D080HN/C1:5 |
|---|---|---|---|---|---|---|
| Brand | Renesas Electronics | Renesas Electronics | Renesas Electronics | Renesas Electronics | Renesas Electronics | Renesas Electronics |
| Package | 56-VFQFN exposed pad (HVQFN-56, 8x8 mm) | 56-VFQFN exposed pad (HVQFN-56, 8x8 mm) - same | 56-VFQFN exposed pad (HVQFN-56, 8x8 mm) - same | 56-VFQFN exposed pad (HVQFN-56, 8x8 mm) - same | 56-VFQFN exposed pad (HVQFN-56, 8x8 mm) - same | 56-VFQFN exposed pad (HVQFN-56, 8x8 mm) - same |
| Resolution | 16 bit | 16 bit | 16 bit | 16 bit | 16 bit | 10 bit (lower) |
| Max Sample Rate | 80 MSPS | 65 MSPS (-18.75%) | 105 MSPS (+31%) | 125 MSPS (+56%) | 80 MSPS (same) | 80 MSPS (same) |
| Number of Channels | 2 (dual) | 2 (dual) | 2 (dual) | 2 (dual) | 2 (dual) | 2 (dual) |
| Output Interface | JESD204A | JESD204A | JESD204A | JESD204A | JESD204A | JESD204A |
| Approximate Unit Price (qty 100) | USD 38.10 | USD ~30-33 (lower throughput discount) | USD ~42-45 (higher throughput premium) | USD ~50-55 (highest throughput premium) | USD ~38 (same die) | USD ~25 (lower resolution) |
关键差异点
- Pin-compatible speed grade across the ADC1613D family （对比 ADC1613D065HN-C1)
- Lower power than the 125 MSPS grade at identical footprint （对比 ADC1613D125HN-C1)
- Higher resolution than the 10-bit ADC1012D080HN at the same speed （对比 ADC1012D080HN/C1:5)
设计说明
The HVQFN-56 exposed thermal pad must be soldered to a PCB copper pour that occupies at least 1 square cm of continuous copper on the top layer and is stitched with a 4 x 4 grid of 0.3 mm thermal vias to inner ground planes. Estimated: at 80 MSPS, full-clock dual-channel operation, the ADC1613D080HN-C1 dissipates roughly 200-300 mW (typical analog supply current is 1.9 V times <150 mA per datasheet estimates); without the thermal pad stitched, the junction temperature can exceed the 125 C absolute maximum at ambient >85 C. Designers should leave the factory land pattern unchanged and not route signal traces under the thermal pad.
Place all 1.2 V and 3.3 V decoupling capacitors within 5 mm of their respective pins, using a 100 nF X7R bypass for every supply pin and a 10 uF X5R bulk capacitor on each supply rail near the package. The differential clock pair (CLKINP / CLKINN) and the JESD204A CML output pair (DOUTP / DOUTN) must be routed as 100 ohm differential transmission lines with length matching within 0.5 mm; route these on a stripline layer referenced to a solid ground plane for clean 80 MHz and 5 GHz spectra. Avoid crossing the analog input traces under the digital outputs to prevent digital coupling into the ADC front end.
Estimated: the JESD204A subclass 1 deterministic latency requires a SYSREF signal that is phase-aligned to CLKIN; if SYSREF skew exceeds one CLKIN period, the link will intermittently lose synchronisation and produce corrupted output frames. Do not insert a non-zero-length clock buffer between the FPGA and the ADC's CLKIN pins unless the buffer delay is also compensated in the SYSREF path. Also, the part's hardware RESETN assertion of at least 100 ns is required after power supply rails are stable; pulsing RESETN too early leaves SPI registers in an indeterminate state and causes apparent link training failures.
合规信息
RoHS compliance inferred from package datasheet summary; explicit REACH statement, halogen-free status, and conflict-minerals declaration not present in the verified source data - explicitly verify with Renesas product compliance letter for production builds.
