CDK1308BILP40 - 10-bit 40MSPS Ultra-Low Power ADC | MaxLinear
料号： CDK1308BILP40 ✓ 量产中| 数量 | 单价 | 小计 |
|---|---|---|
| 1 | $5.92 | $5.92 |
| 10 | $5.28 | $52.80 |
| 100 | $4.62 | $462.00 |
| 500 | $4.1 | $2,050.00 |
| 1,000 | $3.58 | $3,580.00 |
CDK1308BILP40 概述
An analog-to-digital converter (ADC) is a mixed-signal integrated circuit that converts continuous-time, continuous-amplitude analog signals into discrete digital codes. Within the broader signal chain hierarchy, ADCs sit between analog front-end conditioning (amplifiers, anti-alias filters) and digital processing (FPGA, microcontroller, DSP), making them a critical component in data acquisition systems, imaging, and communications equipment. Ultra-low-power ADCs such as the CDK1308 target portable and battery-powered applications where milliwatts-per-sample directly impact battery life and thermal budgets.
Key features include 25 mW typical power dissipation at 40 MSPS, 61.6 dB SNR at an 8 MHz analog input, internal reference circuitry (eliminating external reference components), a 1.8 V analog core supply, and a separate 1.7 V to 3.6 V digital I/O supply for flexible host interfacing. The device uses a proprietary CMOS architecture with digital error correction, delivering high linearity while keeping die area and power low. Parallel CMOS outputs simplify connection to FPGAs, ASICs, and microcontrollers without requiring an external serializer.
The CDK1308B is pin-compatible with the CDK1307 family, enabling system scalability between 10-bit (CDK1308) and 12-bit (CDK1307) resolutions on the same PCB. This makes the part attractive for medical imaging, portable test equipment, digital oscilloscopes, and IF communications designs where a single hardware platform must support multiple performance tiers.
Typical applications span handheld ultrasound front-ends, digital oscilloscopes, IF sampling for software-defined radio (SDR), and portable industrial inspection cameras. The combination of low power, small QFN footprint, and internal reference simplifies multi-channel designs where board area and BOM cost are constrained.
When designing with the CDK1308BILP40, decouple AVDD and DVDD separately with 1 µF and 100 nF capacitors placed as close to the pins as possible. Drive the analog input through a wideband op-amp or transformer; the input is a switched-capacitor structure that benefits from a low-impedance source to preserve SNR at high input frequencies.
直接替换替代料： CDK1308BILP40 ——相同封装，引脚兼容。需要 PCB 改动的不同封装料号已排除。
本系列中的变体
可与以下型号直接替换的同系列型号： CDK1308BILP40 （相同外形与封装尺寸） ——差异在于 Architecture, Package, Resolution, Manufacturer, Reference.
快速对比工具——选择替代料号进行并排对比：
CDK1307CILP40
✅ 直接替换✓ 有现货
$3.95 / 个
查看数据手册 →CDK1308AILP20
✅ 直接替换📋 参考替代料（不在目录中）
CDK1308CILP65
✅ 直接替换📋 参考替代料（不在目录中）
CDK1308CILP80
✅ 直接替换📋 参考替代料（不在目录中）
CDK1308BILP40 最大额定值与电气特性
| 分辨率 | 10 bits |
| Sampling Rate (BILP40 speed grade) | 40 MSPS |
| Family Speed Grades | 20 / 40 / 65 / 80 MSPS |
| Power Dissipation | 25 mW (typical at 40 MSPS) |
| SNR | 61.6 dB at Fin = 8 MHz |
| Analog Supply Voltage (AVDD) | 1.8 V |
| Digital I/O Supply Voltage (DVDD) | 1.7 V to 3.6 V |
| Reference | Internal |
| Output Interface | Parallel CMOS |
| Architecture | Proprietary CMOS with digital error correction |
| 封装 | 40-pin QFN (LP40) |
| Pin Compatibility | Pin-compatible with CDK1307 (12-bit) family |
| Input Type | Single-ended analog input |
| RoHS 状态 | Compliant |
| Manufacturer | Exar Corporation (now MaxLinear) |
CDK1308BILP40 引脚配置
| 引脚 1 | AVDD — Analog supply voltage (1.8 V) |
| 引脚 2 | GND — Ground |
| 引脚 3 | AIN — Analog input |
| 引脚 4 | AVDD — Analog supply voltage (1.8 V) |
| 引脚 5 | GND — Ground |
| 引脚 6 | REF — Internal reference decoupling |
| 引脚 7 | GND — Ground |
| 引脚 8 | CLKP — Clock input positive |
| 引脚 9 | CLKN — Clock input negative / complementary |
| 引脚 10 | DVDD — Digital I/O supply (1.7-3.6 V) |
| 引脚 11 | GND — Ground |
| 引脚 12 | D0 — Data output bit 0 (LSB) |
| 引脚 13 | D1 — Data output bit 1 |
| 引脚 14 | D2 — Data output bit 2 |
| 引脚 15 | D3 — Data output bit 3 |
| 引脚 16 | D4 — Data output bit 4 |
| 引脚 17 | D5 — Data output bit 5 |
| 引脚 18 | D6 — Data output bit 6 |
| 引脚 19 | D7 — Data output bit 7 |
| 引脚 20 | D8 — Data output bit 8 |
| 引脚 21 | D9 — Data output bit 9 (MSB) |
| 引脚 22 | GND — Ground |
| 引脚 23 | DVDD — Digital I/O supply (1.7-3.6 V) |
| 引脚 24 | OE — Output enable |
| 引脚 25 | GND — Ground |
| 引脚 26 | PD — Power-down control |
| 引脚 27 | GND — Ground |
| 引脚 28 | NC — Not connected (per datasheet) |
| 引脚 29 | NC — Not connected (per datasheet) |
| 引脚 30 | AVDD — Analog supply voltage (1.8 V) |
| 引脚 31 | GND — Ground |
| 引脚 32 | NC — Not connected (per datasheet) |
| 引脚 33 | NC — Not connected (per datasheet) |
| 引脚 34 | AVDD — Analog supply voltage (1.8 V) |
| 引脚 35 | GND — Ground |
| 引脚 36 | NC — Not connected (per datasheet) |
| 引脚 37 | NC — Not connected (per datasheet) |
| 引脚 38 | AVDD — Analog supply voltage (1.8 V) |
| 引脚 39 | GND — Ground |
| 引脚 40 | EP — Exposed pad - thermal/ground connection |
典型应用
CDK1308BILP40 适用于 6 应用s: Portable Digital Oscilloscope Front-End, Handheld Medical Imaging (Ultrasound / Doppler), IF Sampling for Software-Defined Radio (SDR), Portable Test & Measurement Equipment, Industrial Inspection Camera Digitizer, Low-Cost Communications IF Digitizer.
Portable Digital Oscilloscope Front-End
The CDK1308BILP40 fits handheld oscilloscope front-ends where its 25 mW typical dissipation at 40 MSPS keeps the battery and thermal budget manageable. Its 61.6 dB SNR at 8 MHz input preserves signal fidelity when digitizing repetitive waveforms up to several MHz, while the parallel CMOS output avoids the latency and clock-recovery overhead of LVDS/serial interfaces. The internal reference eliminates a dedicated reference IC, reducing BOM cost on a tightly-packed multi-channel scope motherboard. The 40-pin QFN footprint with exposed pad enables compact layouts where every square millimeter matters.
推荐
Handheld Medical Imaging (Ultrasound / Doppler)
In portable ultrasound carts, the CDK1308BILP40's 1.8 V analog supply and 25 mW dissipation reduce total system power and battery heating. Its 10-bit resolution and 61.6 dB SNR support diagnostic imaging of shallow structures when paired with a low-noise TGC amplifier. Parallel CMOS outputs stream samples directly into an FPGA beamformer without serializer-induced latency, which is critical for real-time B-mode imaging. Internal reference circuitry shrinks the per-channel BOM, supporting dense multi-element probe designs.
推荐
IF Sampling for Software-Defined Radio (SDR)
The CDK1308BILP40's 40 MSPS sampling rate comfortably digitizes low-IF signals up to approximately 18 MHz (Nyquist), making it well-suited to amateur-radio and shortwave SDR receivers where 10-bit dynamic range is sufficient. Its 1.7-3.6 V digital I/O supply interfaces directly to 1.8 V or 3.3 V FPGA fabrics without level shifters, simplifying SDR shield designs. The internal reference and low power simplify battery-powered QRP portable SDR rigs.
推荐
Portable Test & Measurement Equipment
Handheld spectrum analyzers, logic-analyzer probes, and field-installable cable testers benefit from the CDK1308BILP40's 25 mW dissipation, which extends battery runtime between charges. The internal reference eliminates drift-inducing external references in field-temperature conditions. Parallel CMOS outputs can be multiplexed into an MCU DMA stream, simplifying the digital back-end on cost-sensitive test instruments. Pin compatibility with the CDK1307 family lets a single PCB serve both 10-bit and 12-bit product variants.
推荐
Industrial Inspection Camera Digitizer
In machine-vision and borescope inspection cameras, the CDK1308BILP40 digitizes analog video from CMOS image sensors at rates up to 40 MSPS, sufficient for standard-definition imaging pipelines. The 1.8 V core supply is compatible with modern low-voltage image sensors, reducing power-rail complexity. Its low heat output supports sealed, fan-less enclosures used in food, pharma, and hazardous-area inspection equipment.
推荐
Low-Cost Communications IF Digitizer
For narrowband IF strips in point-to-point microwave links and telemetry receivers, the CDK1308BILP40 offers 10-bit dynamic range with 25 mW dissipation, supporting dense multi-channel receiver designs. The internal reference and small QFN package enable compact daughtercards, while the parallel CMOS output simplifies connection to low-cost microcontrollers used in modem subsystems.
推荐
推荐产品汇总
工程参考数据： CDK1308BILP40 ——对比、设计指导和合规信息。
选型指南
与替代料对比
| 参数 | 本产品 | CDK1307CILP40 | CDK1308AILP20 | CDK1308CILP65 | CDK1308CILP80 | ADS901E/1KG4 |
|---|---|---|---|---|---|---|
| Package | 40-pin QFN (LP40) | 40-pin QFN (LP40) - same | 40-pin QFN (LP40) - same | 40-pin QFN (LP40) - same | 40-pin QFN (LP40) - same | 28-pin SSOP (different package) |
| Brand | MaxLinear (Exar) | MaxLinear (Exar) | MaxLinear (Exar) | MaxLinear (Exar) | MaxLinear (Exar) | Texas Instruments |
| Resolution | 10 bits | 12 bits | 10 bits | 10 bits | 10 bits | 10 bits |
| Max Sample Rate | 40 MSPS | 40 MSPS | 20 MSPS | 65 MSPS | 80 MSPS | 20 MSPS |
| Pin-Compatible Family Upgrade Path | CDK1307 (12-bit) / CDK1308C (65-80 MSPS) | 12-bit upgrade | Lower-power 20 MSPS drop | 65 MSPS upgrade | 80 MSPS upgrade | Different package, not pin-compatible |
关键差异点
- Ultra-low 25 mW dissipation at 40 MSPS for battery-powered designs （对比 ADS901E/1KG4)
- Pin-compatible resolution and speed upgrade path within same QFN footprint （对比 ADS901E/1KG4)
- Internal reference eliminates external reference BOM （对比 ADS901E/1KG4)
设计说明
Estimated: at 1.8 V AVDD and 25 mW typical dissipation, the supply current is approximately 13.9 mA from AVDD plus the additional current drawn from DVDD at the chosen I/O voltage. Decouple AVDD and DVDD separately with a 1 µF ceramic bulk plus a 100 nF high-frequency bypass placed within 5 mm of each supply pin to suppress switching noise coupling into the analog front-end. Power-down (PD) pin reduces dissipation to microampere range when held low - use this aggressively in battery-powered designs between acquisitions.
The analog input is a switched-capacitor structure; drive it through a wideband op-amp or RF transformer with source impedance below 50 ohm at the highest input frequency of interest. Mismatched impedance at the analog input will degrade SNR at high Fin. Route the differential clock (CLKP/CLKN) as a matched-length pair and keep it physically separated from the analog input and parallel CMOS data outputs to avoid clock-feed-through coupling into the analog path.
The 40-pin QFN (LP40) exposed pad must be soldered to a continuous ground plane for thermal dissipation and electrical reference. Provide at least four thermal vias in the EP land pattern (0.3 mm drill, 1 mm pitch) to drop junction-to-ambient thermal resistance. Keep all analog traces on the top layer with a continuous ground plane beneath, and route parallel CMOS data outputs as a matched-length bus (within 2 mm of each other) to minimize skew into the receiving FPGA or MCU.
Do not exceed 1.8 V on AVDD - the part is not tolerant of higher analog supply voltages. DVDD range is 1.7-3.6 V but must be sequenced after AVDD to avoid latch-up. The internal reference is bypassed at the REF pin - do not load this pin with external circuitry. When upgrading to the pin-compatible CDK1307 (12-bit) family, re-evaluate SNR and linearity budgets because the 12-bit version has different analog input common-mode and gain characteristics.
合规信息
RoHS and REACH compliance per MaxLinear (formerly Exar Corporation) product page. Not AEC-Q100 qualified - this part is targeted at industrial, medical, and consumer equipment, not automotive. Halogen-free status not stated in the verified web data - flagged as unknown.
