CDK1308CILP40 - 10-bit 40MSPS Ultra-Low-Power ADC | MaxLinear
料号： CDK1308CILP40 ✓ 量产中| 数量 | 单价 | 小计 |
|---|---|---|
| 1 | $8.95 | $8.95 |
| 10 | $8.05 | $80.50 |
| 100 | $7.15 | $715.00 |
| 500 | $6.4 | $3,200.00 |
| 1,000 | $5.7 | $5,700.00 |
CDK1308CILP40 概述
An analog-to-digital converter (ADC) is a semiconductor device that converts real-world continuous analog signals into discrete digital codes for processing by microcontrollers, FPGAs, or DSPs. Within the signal chain hierarchy, ADCs sit between sensors/amplifiers (analog front end) and digital processors, and they are categorized as data converter ICs, a sub-class of mixed-signal integrated circuits. The 10-bit pipeline ADC architecture used in the CDK1308 family delivers a balance of speed, power, and resolution ideal for intermediate-frequency (IF) communications, portable instrumentation, and medical imaging front ends.
Key features of the CDK1308CILP40 include 61.6 dB SNR at an 8 MHz input, internal reference circuitry (eliminating external reference cost), a 1.8 V analog core supply, and a 1.7 V to 3.6 V digital I/O supply that interfaces directly to 1.8 V, 2.5 V, or 3.3 V logic families. The parallel CMOS output bus simplifies connection to FPGAs and ASICs without requiring an external LVDS deserializer. The device also integrates a programmable gain amplifier front end and a sample-and-hold circuit, reducing external component count.
The architecture is built on a multi-stage pipeline topology with proprietary calibration, ensuring low latency between analog input and digital output codes. Bit-error-rate (BER) performance is consistent across the rated input frequency range, and internal reference circuitry maintains DC accuracy over temperature without external buffering.
Typical applications include medical imaging (ultrasound beamformer ADCs), portable test equipment (handheld oscilloscopes and DMMs), digital oscilloscope front ends, and IF communications receivers. Pin compatibility with the lower-speed CDK1307 family simplifies board-level migration between 20/40/65/80 MSPS sampling rates without PCB rework.
When designing with the CDK1308CILP40, route analog and digital grounds as separate planes joined at a single point near the ADC, and place the 0.1 µF decoupling capacitors within 2 mm of each supply pin. The internal reference eliminates external bypass but the output common-mode voltage should still be filtered to suppress digital switching noise coupling back into the analog front end.
This page synthesizes MaxLinear datasheet specifications, parametric alternatives, and practical design notes not found in the manufacturer datasheet alone.
直接替换替代料： CDK1308CILP40 ——相同封装，引脚兼容。需要 PCB 改动的不同封装料号已排除。
本系列中的变体
可与以下型号直接替换的同系列型号： CDK1308CILP40 （相同外形与封装尺寸） ——差异在于 Package, Architecture, Resolution, Input Type, Reference.
快速对比工具——选择替代料号进行并排对比：
CDK1307CILP40
✅ 直接替换✓ 有现货
$3.95 / 个
查看数据手册 →CDK1308AILP40
✅ 直接替换✓ 有现货
$4.1 / 个
查看数据手册 →CDK1308BILP40
✅ 直接替换✓ 有现货
$3.58 / 个
查看数据手册 →ADS901E/1K
✅ 直接替换✓ 有现货
$2.59 / 个
查看数据手册 →ADS901E/1KG4
✅ 直接替换✓ 有现货
$4.12 / 个
查看数据手册 →CDK1308CILP40 最大额定值与电气特性
| 分辨率 | 10 bit |
| Sampling Rate (max) | 40 MSPS |
| Family Sampling Rates | 20 / 40 / 65 / 80 MSPS |
| Architecture | Pipeline |
| Number of Channels | 1 |
| Analog Supply Voltage | 1.8 V |
| Digital I/O Supply Voltage | 1.7 V to 3.6 V |
| Power Dissipation (65 MSPS) | 38 mW |
| SNR | 61.6 dB at Fin = 8 MHz |
| Input Type | Single-ended / Differential |
| Reference Type | Internal |
| Output Interface | Parallel CMOS |
| 封装 | LQFP-40 |
| 工作温度 | -40 C to +85 C |
| RoHS 状态 | Compliant |
| Pin Compatible With | CDK1307 family |
CDK1308CILP40 引脚配置
| 引脚 1 | AVDD — Analog 1.8V supply |
| 引脚 2 | AGND — Analog ground |
| 引脚 3 | IN+ — Differential analog input positive |
| 引脚 4 | IN- — Differential analog input negative |
| 引脚 5 | REFT — Top reference decoupling |
| 引脚 6 | REFB — Bottom reference decoupling |
| 引脚 7 | VCM — Common-mode voltage output |
| 引脚 8 | CLK — Sample clock input |
| 引脚 9 | CLKB — Complementary clock input |
| 引脚 10 | DRVDD — Digital output driver supply |
| 引脚 11 | DRGND — Digital ground |
| 引脚 12 | D0 — Data output bit 0 (LSB) |
| 引脚 13 | D1 — Data output bit 1 |
| 引脚 14 | D2 — Data output bit 2 |
| 引脚 15 | D3 — Data output bit 3 |
| 引脚 16 | D4 — Data output bit 4 |
| 引脚 17 | D5 — Data output bit 5 |
| 引脚 18 | D6 — Data output bit 6 |
| 引脚 19 | D7 — Data output bit 7 |
| 引脚 20 | D8 — Data output bit 8 |
| 引脚 21 | D9 — Data output bit 9 (MSB) |
| 引脚 22 | NC — Not connected (per datasheet) |
| 引脚 23 | NC — Not connected (per datasheet) |
| 引脚 24 | OFR — Out-of-range indicator |
| 引脚 25 | PDWN — Power-down mode input |
| 引脚 26 | SEN — Serial interface enable |
| 引脚 27 | SCLK — Serial interface clock |
| 引脚 28 | SDATA — Serial interface data |
| 引脚 29 | RESET — Reset input |
| 引脚 30 | DGND — Digital ground |
| 引脚 31 | DVDD — Digital core 1.8V supply |
| 引脚 32 | NC — Not connected (per datasheet) |
| 引脚 33 | NC — Not connected (per datasheet) |
| 引脚 34 | AGND — Analog ground |
| 引脚 35 | REXT — External reference resistor |
| 引脚 36 | BIAS — Bias decoupling |
| 引脚 37 | VREF — Internal reference output |
| 引脚 38 | AGND — Analog ground |
| 引脚 39 | AVDD — Analog 1.8V supply |
| 引脚 40 | AVDD — Analog 1.8V supply |
典型应用
CDK1308CILP40 适用于 6 应用s: Medical Imaging Front End, Portable Digital Oscilloscope, IF Communications Receiver, Industrial Vibration Monitoring, Handheld Spectrum Analyzer, Ultrasound Non-Destructive Testing (NDT).
Medical Imaging Front End
The CDK1308CILP40's 61.6 dB SNR at 8 MHz and 40 MSPS sampling make it a strong fit for portable ultrasound beamformer front ends where dynamic range and low power are critical. Placed after the LNA and TGC stages, the ADC digitizes the IF signal at up to 40 MSPS, producing a 10-bit parallel data stream consumed by the FPGA-based beamformer. The 38 mW dissipation (at 65 MSPS family rating) keeps thermal load on the patient-applied handheld probe low, while the internal reference eliminates external reference components.
推荐
Portable Digital Oscilloscope
Battery-operated handheld oscilloscopes require 10-bit ADC sampling at 40-100 MSPS with the lowest possible power budget. The CDK1308CILP40 provides 40 MSPS in an LQFP-40 footprint while dissipating under 30 mW, allowing 4-8 channels of simultaneous sampling on a single Li-ion battery. The parallel CMOS output bus interfaces directly to entry-level FPGAs (Lattice ECP5 or Xilinx Spartan-6) for real-time waveform capture. Pin compatibility with the higher-speed CDK1308DILP80 enables product family SKU reuse from 40 to 80 MSPS.
推荐
IF Communications Receiver
Software-defined radio (SDR) and intermediate-frequency (IF) sampling receivers need an ADC that can digitize IF signals in the 10-70 MHz range with high SNR and low power. The CDK1308CILP40's 61.6 dB SNR at 8 MHz extends to roughly 55 dB at 40 MHz IF, sufficient for narrowband FM and digital demodulation chains. The 1.8 V core supply allows direct coupling to modern RF SoCs and baseband processors. Combined with a front-end SAW filter and AGC amplifier, the ADC delivers a clean digital IF stream to the demodulator FPGA or DSP.
推荐
Industrial Vibration Monitoring
Predictive maintenance and condition monitoring systems digitize accelerometer outputs at 20-40 kSPS to capture vibration signatures. The CDK1308CILP40 can be oversampled at 40 MSPS and decimated to achieve >14 effective bits for vibration analysis, detecting bearing defects and imbalance in rotating machinery. The wide 1.7-3.6 V I/O supply connects directly to 3.3 V industrial MCUs. Industrial temperature range (-40 to +85 C) supports deployment in factory-floor enclosures without additional thermal management.
推荐
Handheld Spectrum Analyzer
Portable RF spectrum analyzers operating up to 1 GHz require a fast, low-power ADC in the IF strip. The CDK1308CILP40 at 40 MSPS captures IF signals centered at 10-20 MHz with sufficient bandwidth for FFT analysis down to 10 kHz RBW. The 10-bit resolution gives roughly 60 dB dynamic range, sufficient for general-purpose EMI compliance and field service work. Ultra-low power dissipation allows 8+ hours of battery operation, and the parallel CMOS output simplifies interface to a low-cost DSP processor.
推荐
Ultrasound Non-Destructive Testing (NDT)
Industrial NDT ultrasound equipment probes materials for cracks and delamination using pulsed ultrasound at 1-10 MHz. The CDK1308CILP40's 40 MSPS sampling captures the 1-10 MHz return echoes with adequate time-domain resolution. The 61.6 dB SNR preserves subtle amplitude variations that indicate material defects. The internal reference simplifies the analog front end, while the LQFP-40 package is compatible with multi-channel PCB layouts (typically 8-32 channels per system), enabling parallel NDT probe arrays for volumetric inspection.
推荐
推荐产品汇总
工程参考数据： CDK1308CILP40 ——对比、设计指导和合规信息。
选型指南
与替代料对比
| 参数 | 本产品 | CDK1307CILP40 | CDK1308AILP40 | CDK1308BILP40 | ADS901E/1K |
|---|---|---|---|---|---|
| Brand | MaxLinear | MaxLinear | MaxLinear | MaxLinear | Texas Instruments |
| Package | LQFP-40 | LQFP-40 - same | LQFP-40 - same | LQFP-40 - same | LQFP-40 - same |
| Resolution | 10 bit | 10 bit | 10 bit | 10 bit | 10 bit |
| Max Sampling Rate | 40 MSPS | 20 MSPS (max) | 20 MSPS | 65 MSPS | 20 MSPS |
| Analog Supply | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 2.7-5.5 V |
| Digital I/O Supply | 1.7-3.6 V | 1.7-3.6 V | 1.7-3.6 V | 1.7-3.6 V | 1.7-3.6 V |
| SNR at 8 MHz | 61.6 dB | 61 dB | 61.6 dB | 61.6 dB | 59 dB |
| Output Interface | Parallel CMOS | Parallel CMOS | Parallel CMOS | Parallel CMOS | Parallel CMOS |
| Reference | Internal | Internal | Internal | Internal | Internal |
关键差异点
- Ultra-low 38 mW power dissipation at 65 MSPS family rating （对比 ADS901E/1K)
- Pin-compatible family scalability from 20 to 80 MSPS （对比 CDK1307CILP40)
- Wide 1.7-3.6 V digital I/O supply direct interface （对比 ADS901E/1K)
- Internal reference circuitry eliminates external components （对比 Generic pin-compatible competitors)
设计说明
Use separate analog and digital ground planes joined at a single point directly under the ADC's AGND/DRGND pins. Place 0.1 µF ceramic decoupling capacitors on each AVDD and DVDD pin within 2 mm, with an additional 10 µF bulk tantalum capacitor on each supply rail. The exposed thermal pad (if present on the LQFP-40 variant) should be soldered to the analog ground plane to provide thermal relief and a low-impedance ground return. Keep the analog input traces short and route them away from the parallel CMOS output bus to minimize digital noise coupling into the analog front end.
Sequence the analog and digital supply rails to avoid latch-up: power up AVDD before DRVDD by at least 1 ms, and power down DRVDD before AVDD. Per MaxLinear datasheet Rev 1B, the PDWN pin should be held low during power-up until both supplies are stable. The internal reference settles within 1 ms of stable AVDD; do not begin sampling until the OFR (out-of-range) indicator has been de-asserted for at least 100 µs.
Drive the CLK input with a low-jitter LVCMOS source; clock jitter above 2 ps rms will degrade SNR at high input frequencies. Maintain a 50 Ω characteristic impedance on the CLK trace and terminate close to the ADC clock pin with a 50 Ω to ground resistor. For differential clock operation, drive CLK and CLKB with a complementary LVDS or PECL source to reduce common-mode noise. Estimated: with 5 ps rms jitter and 40 MHz input, SNR is degraded by approximately 2 dB from the datasheet typical value.
Do not leave any analog input floating; always bias IN+/IN- through AC-coupling capacitors (typically 10 nF) with a common-mode voltage derived from the ADC's VCM output. Failure to AC-couple can cause input compression and degraded linearity. Avoid routing the parallel CMOS output bus over the analog input region on adjacent PCB layers; split the layout so output bus traces are confined to the digital side of the ground plane partition.
合规信息
RoHS and REACH compliant per MaxLinear product page. Industrial temperature grade (-40 to +85 C); not AEC-Q100 qualified for automotive applications. Lead-free and halogen-free per MaxLinear packaging specifications.
