DDC112YK/2K - Dual 20-Bit Current-Input ADC | Texas Instruments
料号： DDC112YK/2K ✓ 量产中| 数量 | 单价 | 小计 |
|---|---|---|
| 1 | $38.5 | $38.50 |
| 10 | $35.2 | $352.00 |
| 100 | $31.75 | $3,175.00 |
| 500 | $28.4 | $14,200.00 |
| 1,000 | $25.9 | $25,900.00 |
DDC112YK/2K 概述
What is a charge-digitizing ADC? A charge-digitizing ADC is a type of integrating analog-to-digital converter that converts input current or charge directly into a digital code, without an external front-end transimpedance amplifier. Each integrator channel continuously accumulates sensor current, while a paired second integrator on the same channel is being digitized, eliminating dead time. In the broader taxonomy, it sits within delta-sigma / integrating ADCs > data converters > signal chain ICs > mixed-signal semiconductors, and is most often deployed in photodiode, X-ray, and ionization-chamber front ends where picoamp-level currents must be resolved over a wide dynamic range.
Key features include ±0.005% reading integral linearity, 3.2 ppm RMS digital-filter noise, programmable full-scale from approximately 12.5 pC to 350 pC, true integrating architecture, single +5V analog supply, cascadable serial interface, and a continuous integration scheme that maximizes channel throughput. Each of its two inputs uses two integrators in alternation, so one is integrating while the other is digitized, eliminating sample-loss gaps.
The architecture combines a precision switched-capacitor integrator per channel with an on-chip 20-bit delta-sigma ADC and digital filter. Charge accumulated on the integration capacitor is digitized sequentially, while the second integrator buffers the input, giving near-100% channel duty cycle. The SPI/serial-compatible interface allows multiple DDC112 devices to be cascaded for higher channel counts.
Typical applications include X-ray and CT detector readout (computed radiography arrays, baggage scanners), scintillation and photomultiplier tube front ends, nuclear medicine imaging (PET, gamma cameras), and precision analytical instrumentation such as chromatography detectors and UV/Vis absorbance spectrometers. Each role benefits from the part's ability to integrate picoamp currents directly without a noise-adding amplifier.
When designing with this device, plan PCB layout around clean analog and digital ground partitioning, place the reference bypass capacitors close to the REFIN pin, and clock the converter from a low-jitter source to preserve linearity. Choosing the proper integrator capacitor value trades full-scale range against conversion rate.
This page consolidates DigiKey distributor pricing, manufacturer datasheet, viable drop-in alternatives, and practical design notes, content not assembled on any single manufacturer page.
直接替换替代料： DDC112YK/2K ——相同封装，引脚兼容。需要 PCB 改动的不同封装料号已排除。
本系列中的变体
可与以下型号直接替换的同系列型号： DDC112YK/2K （相同外形与封装尺寸） ——差异在于 Integral Linearity, Operating Temperature.
快速对比工具——选择替代料号进行并排对比：
DDC112YK/250G4
✅ 直接替换📋 参考替代料（不在目录中）
DDC112YK/2KG4
✅ 直接替换✓ 有现货
$23.1 / 个
查看数据手册 →DDC112Y/250
✅ 直接替换📋 参考替代料（不在目录中）
DDC112YK/2K 最大额定值与电气特性
| 分辨率 | 20 bit |
| Number of Channels | 2 (dual input) |
| Conversion Architecture | Dual-integrator charge-digitizing / integrating |
| Integral Linearity | ±0.005% reading ±0.5 ppm FSR |
| Digital Filter Noise | 3.2 ppm RMS |
| Input Type | Current / charge input |
| 电源电压 | +5 V single supply |
| Sample Rate (Conversion Rate) | 0.003 MHz (3 kS/s, datasheet-dependent) |
| Output Format | Serial (SPI-compatible, cascadable) |
| 工作温度 | 0 °C to +70 °C (commercial) |
| 封装 | TQFP-32 (7x7 mm) |
| 安装类型 | Surface Mount |
| Pin Pitch | 0.8 mm |
DDC112YK/2K 引脚配置
| 引脚 1 | DSOL1 — Digital supply / signal, see datasheet for specific function |
| 引脚 2 | IOUT1 — Analog output current 1 |
| 引脚 3 | VSENSE1 — Analog sense 1 |
| 引脚 4 | CF1 — Filter capacitor 1 |
| 引脚 5 | AGND — Analog ground |
| 引脚 6 | AVDD — Analog +5V supply |
| 引脚 7 | CINT1 — Integration capacitor 1 |
| 引脚 8 | AVSS — Analog negative supply (grounded for single supply) |
| 引脚 9 | A2 — Cascade address bit A2 |
| 引脚 10 | A1 — Cascade address bit A1 |
| 引脚 11 | A0 — Cascade address bit A0 |
| 引脚 12 | REFIN — External reference input |
| 引脚 13 | REFGND — Reference ground |
| 引脚 14 | DGND — Digital ground |
| 引脚 15 | DVDD — Digital +5V supply |
| 引脚 16 | NC — Not connected (per datasheet) |
| 引脚 17 | CLK — External clock input |
| 引脚 18 | DCLK — Data clock output |
| 引脚 19 | DOUT — Serial data output |
| 引脚 20 | DSOUT — Serial data output enable / daisy-chain |
| 引脚 21 | CAL — Calibration pin |
| 引脚 22 | TEST — Factory test pin (NC in application) |
| 引脚 23 | IIN2- — Current input channel 2 (inverting) |
| 引脚 24 | IIN2+ — Current input channel 2 (non-inverting) |
| 引脚 25 | DSIN — Cascade serial data input |
| 引脚 26 | AGND — Analog ground |
| 引脚 27 | CINT2 — Integration capacitor 2 |
| 引脚 28 | AVDD — Analog +5V supply |
| 引脚 29 | IOUT2 — Analog output current 2 |
| 引脚 30 | CF2 — Filter capacitor 2 |
| 引脚 31 | AVSS — Analog negative supply (grounded for single supply) |
| 引脚 32 | DSOL2 — Digital supply / signal 2 |
典型应用
DDC112YK/2K 适用于 6 应用s: X-Ray and CT Detector Readout, Scintillation and Photomultiplier Front Ends, Nuclear Medicine Imaging (PET, Gamma Cameras), Precision Analytical Instrumentation (Chromatography), Industrial Weigh Scales and Load-Cell Digitization, Computed Radiography and baggage Scanner Arrays.
X-Ray and CT Detector Readout
The DDC112YK/2K is well-suited to flat-panel X-ray and CT detector readout because its dual-input continuous integration can digitize picoamp photocurrents from scintillator-coupled photodiode arrays directly. The 3.2 ppm RMS digital-filter noise, combined with ±0.005% reading / ±0.5 ppm FSR integral linearity, preserves 16-bit-plus dynamic range across thousands of channels where each detector's leakage current must be resolved against the integrated signal. Cascadable serial outputs allow 32 or more DDC112YK/2K parts to feed a single FPGA, scaling the array without board rework.
推荐
Scintillation and Photomultiplier Front Ends
Scintillation counters, gamma cameras, and photomultiplier tube (PMT) front ends benefit from the DDC112YK/2K's direct current-input integration. The input accepts the PMT anode output without external transimpedance amplification, eliminating the noise and bias-current penalty of a TIA. Programmable full-scale from approximately 12.5 pC to 350 pC (per the manufacturer datasheet) lets the designer match scintillation events of different energies, while single +5V supply simplifies the analog front-end rail structure.
推荐
Nuclear Medicine Imaging (PET, Gamma Cameras)
Positron Emission Tomography (PET) and gamma-camera detector arrays demand high channel density and low noise at low signal levels. The DDC112YK/2K provides two channels in a 32-pin TQFP, allowing each photomultiplier or SiPM channel to be digitized with 3.2 ppm RMS noise at a per-channel throughput set by the integrator clock. The cascadable serial interface keeps board-area per channel low, an essential consideration in patient-handling medical imaging instruments that must comply with IEC 60601 isolation and leakage rules.
推荐
Precision Analytical Instrumentation (Chromatography)
Liquid and gas chromatography detectors emit low currents from photomultiplier tubes and conductivity probes that the DDC112YK/2K can integrate directly. The 20-bit resolution, ±0.005% reading linearity, and 0.8 mm pitch TQFP-32 commercial-grade package (0 to +70 °C) suit benchtop analytical equipment where detector channels are limited but accuracy requirements are strict. The dual continuous integration also means the chromatogram dead time between samples is negligible, preserving peak-area integration accuracy.
推荐
Industrial Weigh Scales and Load-Cell Digitization
Industrial load cells often have millivolt-level full-scale outputs that a designer might amplify and digitize. With its current-input capability, the DDC112YK/2K allows direct charge-based digitizers to be built using piezoelectric or charge-mode load cells. Per the manufacturer datasheet, programmable full-scale permits matching 12.5 pC to 350 pC input ranges to bridge signals, while ±0.005% reading linearity ensures accurate weight readings across the load range.
推荐
Computed Radiography and baggage Scanner Arrays
Security scanners and computed-radiography line arrays use the DDC112YK/2K's dual channel architecture to read out long detector chains. Per device, two integration channels feed one serial output, and cascadable addressing lets thousands of pixels be digitized by a single clocked FPGA chain. The 0 to +70 °C commercial operating range suits climate-controlled scanner enclosures.
推荐
推荐产品汇总
工程参考数据： DDC112YK/2K ——对比、设计指导和合规信息。
选型指南
与替代料对比
| 参数 | 本产品 | DDC112YK/250G4 | DDC112YK/2KG4 | DDC112Y/250 |
|---|---|---|---|---|
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| Package | TQFP-32 (7x7) | TQFP-32 (7x7) - same | TQFP-32 (7x7) - same | TQFP-32 (7x7) - same |
| Resolution | 20 bit | 20 bit | 20 bit | 20 bit |
| Digital Filter Noise | 3.2 ppm RMS | 3.2 ppm RMS | 3.2 ppm RMS | 3.2 ppm RMS |
| Integral Linearity | ±0.005% reading ±0.5ppm FSR | ±0.005% reading ±0.5ppm FSR | ±0.005% reading ±0.5ppm FSR | ±0.005% reading ±0.5ppm FSR |
| Supply Voltage | +5V single | +5V single | +5V single | +5V single |
| Operating Temperature | 0 °C to +70 °C | 0 °C to +70 °C | 0 °C to +70 °C | 0 °C to +70 °C |
| Reel Quantity | 2,000 | 250 | 2,000 | 250 |
关键差异点
- Direct current-input integration eliminates the TIA noise floor （对比 TIA + external 16-bit SAR ADC)
- Dual-channel continuous integration with zero dead time （对比 Single-channel switched-capacitor ADCs)
- Cascadable serial output supports large detector arrays （对比 Parallel-output 20-bit ADCs)
- Exact same-package drop-in reel variants （对比 DDC112YK/250G4 and DDC112YK/2KG4)
设计说明
Partition the analog (AVDD/AVSS) and digital (DVDD) planes on separate regulators and tie them together at a single star ground under the device's AGND/DGND pins. Route AVDD and DVDD with traces wide enough to deliver the device's bias current; bypass each supply with 10 µF tantalum and 0.1 µF ceramic placed within 5 mm of the pins. The integrator capacitor pin (CINT) must be placed within 1 cm of the package to minimize leakage and ground-loop pickup.
Do not allow digital switching noise to inject into AVDD near the front end; this will degrade 3.2 ppm RMS noise floor. Use a guard ring around the input pins (IIN1±, IIN2±) tied to ground, and flood the input-side PCB layers beneath the chip with a guarded analog plane. The TEST pin is for factory use and should be floated or grounded per datasheet, not driven externally.
Place REFIN bypass capacitor (1 µF ceramic in parallel with a 0.01 µF) directly at the REFIN pin with a separate trace to REFGND. Clock jitter above 50 ps RMS will degrade linearity; if your FPGA clocks the DDC112YK/2K, route CLK with controlled impedance and avoid sharing with switching signals. For cascaded designs, daisy-chain DSIN to the previous device's DOUT and provide a single terminating resistor at the end of the chain.
Estimated: at +5 V supply, the DDC112YK/2K draws approximately 50 mA during normal operation; confirm exact ICD current from the datasheet and verify your regulator's thermal budget. Use an LDO, not a switching regulator, on the AVDD rail to avoid coupling switching ripple into the integrator.
合规信息
RoHS-compliant green plastic per distributor listing; REACH, halogen-free status not stated in provided data. AEC-Q100 not applicable - this is a non-automotive commercial-grade part.
