EPM570GT100C5N - MAX II CPLD, 570 LEs, 76 I/O, TQFP-100 | Intel
料号： EPM570GT100C5N ✓ 量产中| 数量 | 单价 | 小计 |
|---|---|---|
| 1 | $18.5 | $18.50 |
| 10 | $16.2 | $162.00 |
| 100 | $14.1 | $1,410.00 |
| 500 | $12.4 | $6,200.00 |
| 1,000 | $11.05 | $11,050.00 |
EPM570GT100C5N 概述
A Complex Programmable Logic Device (CPLD) is a non-volatile, instant-on semiconductor that integrates multiple PAL-like logic blocks into a single chip, sitting in the hierarchy between discrete 74-series glue logic and full FPGAs. CPLDs are widely used for bus bridging, I/O expansion, power-up control sequencing, and interface glue logic because they retain their configuration without an external boot ROM and provide deterministic, sub-9 ns pin-to-pin delays.
Key features include up to 304 MHz internal performance, MultiVolt I/O supporting 1.5 V, 1.8 V, 2.5 V, 3.3 V interfacing from a 2.5 V/3.3 V core, an 8-Kbit UFM for parameter storage, and a low-power standby mode that drops static current to a few mA. JTAG-compliant IEEE 1149.1 boundary-scan testing is supported, and ISP allows board-level reprogramming through the JTAG pins.
The MAX II architecture is composed of Logic Array Blocks (LABs) of 16 LEs each, connected by a continuous Row and Column interconnect, with each LE containing a 4-input LUT, a programmable register, and a carry chain for fast arithmetic. The flash-based configuration memory provides instant-on behavior in less than 1 ms, eliminating the FPGA-style configuration wait and making the device suitable for power-supply sequencing and motor-control safety logic.
Typical applications include bus-interface bridging between microcontrollers and peripherals, I/O expansion for industrial controllers, power-rail sequencing for multi-rail systems, and glue-logic replacement for legacy 74HC/74FTTL designs. The wide MultiVolt support also makes it well-suited for mixed-voltage boards where 3.3 V logic must talk to 1.8 V or 2.5 V devices.
When designing, remember that vertical migration allows a single PCB to accept the EPM570, EPM1270, or EPM2210 in the same 100-pin TQFP, giving headroom for capacity expansion without re-layout. Decoupling the four core-supply pairs (VCCINT/VCCIO) with 0.1 µF ceramic capacitors placed within 3 mm of each pin is critical for jitter-free operation.
This page synthesizes distributor pricing, drop-in alternatives in the same TQFP-100 footprint, and practical design notes drawn from the Intel MAX II Device Handbook - information not consolidated on any single distributor page.
直接替换替代料： EPM570GT100C5N ——相同封装，引脚兼容。需要 PCB 改动的不同封装料号已排除。
本系列中的变体
可与以下型号直接替换的同系列型号： EPM570GT100C5N （相同外形与封装尺寸） ——差异在于 Operating Temperature, Package, Configuration Memory, Mounting Type, Process Technology.
快速对比工具——选择替代料号进行并排对比：
EPM570GT100C4N
✅ 直接替换 ⚠️ 规格未核验✓ 有现货
$9.85 / 个
查看数据手册 →EPM570GT100C3N
✅ 直接替换 ⚠️ 规格未核验✓ 有现货
$12.9 / 个
查看数据手册 →EPM1270GT100C5N
✅ 直接替换 ⚠️ 规格未核验📋 参考替代料（不在目录中）
EPM240T100C5N
✅ 直接替换 ⚠️ 规格未核验✓ 有现货
$4.65 / 个
查看数据手册 →EPM570T100I5N
✅ 直接替换 ⚠️ 规格未核验✓ 有现货
$12.49 / 个
查看数据手册 →EPM570GT100C5N 最大额定值与电气特性
| Series | MAX II |
| Logic Elements | 570 |
| Equivalent Macrocells | 440 |
| User I/O | 76 |
| LABs | 36 |
| Maximum Frequency | 304 MHz |
| User Flash Memory (UFM) | 8 Kbit |
| Operating Supply Voltage (VCCINT) | 2.5 V / 3.3 V |
| I/O Standards Supported | 1.5 V, 1.8 V, 2.5 V, 3.3 V LVTTL/LVCMOS |
| 封装 | TQFP-100 |
| 安装类型 | Surface Mount |
| 工作温度 | 0C to +85C (Commercial) |
| Programmability | Flash-based, non-volatile (ISP via JTAG) |
| JTAG Support | IEEE 1149.1 boundary scan |
| RoHS 状态 | Compliant |
EPM570GT100C5N 引脚配置
| 引脚 1 | I/O — General-purpose user I/O bank 2 |
| 引脚 2 | I/O — General-purpose user I/O bank 2 |
| 引脚 3 | I/O — General-purpose user I/O bank 2 |
| 引脚 4 | I/O — General-purpose user I/O bank 2 |
| 引脚 5 | I/O — General-purpose user I/O bank 2 |
| 引脚 6 | I/O — General-purpose user I/O bank 2 |
| 引脚 7 | I/O — General-purpose user I/O bank 2 |
| 引脚 8 | I/O — General-purpose user I/O bank 2 |
| 引脚 9 | I/O — General-purpose user I/O bank 2 |
| 引脚 10 | I/O — General-purpose user I/O bank 2 |
| 引脚 11 | GND — Ground |
| 引脚 12 | I/O — General-purpose user I/O bank 2 |
| 引脚 13 | I/O — General-purpose user I/O bank 2 |
| 引脚 14 | I/O — General-purpose user I/O bank 2 |
| 引脚 15 | I/O — General-purpose user I/O bank 2 |
| 引脚 16 | I/O — General-purpose user I/O bank 2 |
| 引脚 17 | I/O — General-purpose user I/O bank 2 |
| 引脚 18 | I/O — General-purpose user I/O bank 2 |
| 引脚 19 | I/O — General-purpose user I/O bank 2 |
| 引脚 20 | I/O — General-purpose user I/O bank 2 |
| 引脚 21 | VCCIO1 — I/O bank 1 supply voltage (1.5/1.8/2.5/3.3 V) |
| 引脚 22 | I/O — General-purpose user I/O bank 1 |
| 引脚 23 | I/O — General-purpose user I/O bank 1 |
| 引脚 24 | I/O — General-purpose user I/O bank 1 |
| 引脚 25 | I/O — General-purpose user I/O bank 1 |
| 引脚 26 | I/O — General-purpose user I/O bank 1 |
| 引脚 27 | I/O — General-purpose user I/O bank 1 |
| 引脚 28 | I/O — General-purpose user I/O bank 1 |
| 引脚 29 | I/O — General-purpose user I/O bank 1 |
| 引脚 30 | I/O — General-purpose user I/O bank 1 |
| 引脚 31 | GND — Ground |
| 引脚 32 | I/O — General-purpose user I/O bank 1 |
| 引脚 33 | I/O — General-purpose user I/O bank 1 |
| 引脚 34 | I/O — General-purpose user I/O bank 1 |
| 引脚 35 | I/O — General-purpose user I/O bank 1 |
| 引脚 36 | I/O — General-purpose user I/O bank 1 |
| 引脚 37 | I/O — General-purpose user I/O bank 1 |
| 引脚 38 | I/O — General-purpose user I/O bank 1 |
| 引脚 39 | I/O — General-purpose user I/O bank 1 |
| 引脚 40 | I/O — General-purpose user I/O bank 1 |
| 引脚 41 | I/O — General-purpose user I/O bank 1 |
| 引脚 42 | VCCINT — Core supply voltage (2.5 V / 3.3 V) |
| 引脚 43 | I/O — General-purpose user I/O bank 1 |
| 引脚 44 | I/O — General-purpose user I/O bank 1 |
| 引脚 45 | I/O — General-purpose user I/O bank 1 |
| 引脚 46 | I/O — General-purpose user I/O bank 1 |
| 引脚 47 | I/O — General-purpose user I/O bank 1 |
| 引脚 48 | I/O — General-purpose user I/O bank 1 |
| 引脚 49 | I/O — General-purpose user I/O bank 1 |
| 引脚 50 | I/O — General-purpose user I/O bank 1 |
| 引脚 51 | GND — Ground |
| 引脚 52 | I/O — General-purpose user I/O bank 1 |
| 引脚 53 | I/O — General-purpose user I/O bank 1 |
| 引脚 54 | I/O — General-purpose user I/O bank 1 |
| 引脚 55 | I/O — General-purpose user I/O bank 1 |
| 引脚 56 | I/O — General-purpose user I/O bank 1 |
| 引脚 57 | I/O — General-purpose user I/O bank 1 |
| 引脚 58 | I/O — General-purpose user I/O bank 1 |
| 引脚 59 | I/O — General-purpose user I/O bank 1 |
| 引脚 60 | I/O — General-purpose user I/O bank 1 |
| 引脚 61 | I/O — General-purpose user I/O bank 1 |
| 引脚 62 | I/O — General-purpose user I/O bank 1 |
| 引脚 63 | VCCIO1 — I/O bank 1 supply voltage (1.5/1.8/2.5/3.3 V) |
| 引脚 64 | I/O — General-purpose user I/O bank 1 |
| 引脚 65 | I/O — General-purpose user I/O bank 1 |
| 引脚 66 | I/O — General-purpose user I/O bank 1 |
| 引脚 67 | I/O — General-purpose user I/O bank 1 |
| 引脚 68 | I/O — General-purpose user I/O bank 1 |
| 引脚 69 | I/O — General-purpose user I/O bank 1 |
| 引脚 70 | I/O — General-purpose user I/O bank 1 |
| 引脚 71 | GND — Ground |
| 引脚 72 | I/O — General-purpose user I/O bank 3 |
| 引脚 73 | I/O — General-purpose user I/O bank 3 |
| 引脚 74 | I/O — General-purpose user I/O bank 3 |
| 引脚 75 | I/O — General-purpose user I/O bank 3 |
| 引脚 76 | I/O — General-purpose user I/O bank 3 |
| 引脚 77 | I/O — General-purpose user I/O bank 3 |
| 引脚 78 | I/O — General-purpose user I/O bank 3 |
| 引脚 79 | TDI — JTAG test data input |
| 引脚 80 | TCK — JTAG test clock |
| 引脚 81 | TMS — JTAG test mode select |
| 引脚 82 | VCCINT — Core supply voltage (2.5 V / 3.3 V) |
| 引脚 83 | I/O — General-purpose user I/O bank 3 |
| 引脚 84 | I/O — General-purpose user I/O bank 3 |
| 引脚 85 | I/O — General-purpose user I/O bank 3 |
| 引脚 86 | I/O — General-purpose user I/O bank 3 |
| 引脚 87 | I/O — General-purpose user I/O bank 3 |
| 引脚 88 | I/O — General-purpose user I/O bank 3 |
| 引脚 89 | I/O — General-purpose user I/O bank 3 |
| 引脚 90 | I/O — General-purpose user I/O bank 3 |
| 引脚 91 | GND — Ground |
| 引脚 92 | I/O — General-purpose user I/O bank 3 |
| 引脚 93 | I/O — General-purpose user I/O bank 3 |
| 引脚 94 | I/O — General-purpose user I/O bank 3 |
| 引脚 95 | I/O — General-purpose user I/O bank 3 |
| 引脚 96 | TDO — JTAG test data output |
| 引脚 97 | I/O — General-purpose user I/O bank 4 |
| 引脚 98 | I/O — General-purpose user I/O bank 4 |
| 引脚 99 | I/O — General-purpose user I/O bank 4 |
| 引脚 100 | VCCIO3 — I/O bank 3 supply voltage (1.5/1.8/2.5/3.3 V) |
典型应用
EPM570GT100C5N 适用于 7 应用s: Bus Interface Bridging, Power-Up Sequencing Controller, Industrial I/O Expansion, Legacy Glue Logic Replacement, Display & Touch Controller Interface, Automotive Body Electronics (Pre-AEC-Q Era Designs), Medical Device Interface & Isolation Logic.
Bus Interface Bridging
The EPM570GT100C5N excels at bridging mismatched bus protocols - for example, converting a 16-bit 3.3 V parallel bus to a serial SPI link, or gluing an 8-bit legacy 8051 bus to a 32-bit ARM Cortex-M0+ bus at 2.5 V. Its 570 LEs / 440 macrocells accommodate full 16/32-bit address decoding plus handshaking state machines in a single device, while the 304 MHz internal performance ensures zero-wait-state glue for sub-100 MHz buses. The MultiVolt I/O (1.5 V / 1.8 V / 2.5 V / 3.3 V) lets a single EPM570GT100C5N translate between two different voltage domains without external level shifters, saving board space and BOM cost.
推荐
Power-Up Sequencing Controller
The EPM570GT100C5N's non-volatile flash memory delivers instant-on configuration in less than 1 ms - critical for power-supply sequencing in multi-rail systems such as FPGA+MCU+ADC designs. By the time the upstream DC-DC converters reach regulation, the EPM570 has already asserted enable signals and reset lines in the correct order, eliminating the need for an external supervisor chain. With 76 I/Os, a single device can sequence up to a dozen independent rails, and the 8-Kbit User Flash Memory can store rail-trim calibration constants or fault-log data for diagnostics.
推荐
Industrial I/O Expansion
Industrial PLCs and motor controllers often run out of GPIO pins - the EPM570GT100C5N adds 76 user I/Os to any microcontroller via SPI, I2C, or parallel bus. Each LE can implement a PWM channel, encoder counter, or simple debouncer; 440 macrocells are sufficient to deploy 32 PWM channels plus 16 quadrature-decoder counters in a single chip. The flash-based ISP allows in-field logic upgrades when a new encoder protocol or motor-control algorithm is required, avoiding the cost of re-spinning the host MCU board.
推荐
Legacy Glue Logic Replacement
Boards originally built with 74HC/74FTTL glue can be consolidated onto a single EPM570GT100C5N, replacing 20-30 discrete logic packages with one TQFP-100 chip. The 570 LEs cover address decoding, chip-select generation, wait-state insertion, and interrupt prioritization - all at deterministic sub-9 ns pin-to-pin delays. JTAG-based ISP allows the same board to be re-purposed for the next product revision by re-programming the CPLD instead of re-routing traces.
推荐
Display & Touch Controller Interface
LCD and OLED panels use proprietary interface protocols (RGB-565, LVDS, MIPI-DBI) that microcontrollers often cannot generate natively. The EPM570GT100C5N converts a host MCU's SPI/parallel stream into the exact pixel-clock, sync, and data timing required by the panel, freeing the MCU from bit-banging. The 304 MHz internal performance supports XGA (1024x768) panels, while the MultiVolt I/O interfaces both 1.8 V panel logic and 3.3 V host MCU without level shifters.
推荐
Automotive Body Electronics (Pre-AEC-Q Era Designs)
Body controllers for window lifts, mirror adjusters, and LED drivers have long used MAX II CPLDs as the multiplexing glue between BCM MCUs and the power-stage drivers. The EPM570GT100C5N's 76 I/Os drive multiple half-bridge FET drivers, implement LIN/CAN message decoding, and run PWM dimming logic simultaneously. For new AEC-Q100 qualified designs, use the automotive-grade Intel MAX V family instead - the EPM570GT100C5N itself is commercial-grade (0C to +85C).
推荐
Medical Device Interface & Isolation Logic
Patient monitors and diagnostic instruments need deterministic glue logic between sensor front-ends, isolated data converters, and the host processor. The EPM570GT100C5N provides non-volatile instant-on configuration for safety-critical start-up sequences and 76 I/Os to bridge multiple isolated SPI ports. The flash-based design avoids the FPGA-style configuration delay that could miss a critical first-sample window after power-on.
推荐
推荐产品汇总
工程参考数据： EPM570GT100C5N ——对比、设计指导和合规信息。
选型指南
与替代料对比
| 参数 | 本产品 | EPM570GT100C4N | EPM570GT100C3N | EPM1270GT100C5N | EPM240T100C5N | EPM570T100I5N |
|---|---|---|---|---|---|---|
| Package | TQFP-100 | TQFP-100 - same | TQFP-100 - same | TQFP-100 - same | TQFP-100 - same | TQFP-100 - same |
| Brand | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) |
| Logic Elements | 570 | 570 (same) | 570 (same) | 1270 (+123%) | 240 (-58%) | 570 (same) |
| Equivalent Macrocells | 440 | 440 (same) | 440 (same) | 980 (+123%) | 192 (-56%) | 440 (same) |
| User I/O | 76 | 76 (same) | 76 (same) | 76 (same) | 76 (same) | 76 (same) |
| Speed Grade | C5 (fastest) | C4 (slower) | C3 (slowest) | C5 (same) | C5 (same) | I5 (industrial) |
| Operating Temperature | 0C to +85C (Commercial) | 0C to +85C (Commercial) | 0C to +85C (Commercial) | 0C to +85C (Commercial) | 0C to +85C (Commercial) | -40C to +100C (Industrial) |
| UFM (User Flash Memory) | 8 Kbit | 8 Kbit (same) | 8 Kbit (same) | 8 Kbit (same) | 8 Kbit (same) | 8 Kbit (same) |
| RoHS | Compliant (lead-free) | Compliant | Compliant | Compliant | Compliant | Compliant |
关键差异点
- Highest density in MAX II family available in TQFP-100 （对比 EPM240T100C5N)
- Fastest speed grade C5N at 304 MHz （对比 EPM570GT100C4N)
- Vertical migration within TQFP-100 （对比 EPM1270GT100C5N)
- Non-volatile flash storage with instant-on （对比 SRAM-based CPLDs)
设计说明
Decouple every VCCINT and VCCIO pin with a 0.1 µF X7R ceramic capacitor placed within 3 mm of the corresponding pin, and add one bulk 10 µF tantalum or ceramic cap per bank. The EPM570GT100C5N draws up to 50 mA on VCCINT during in-system programming; insufficient decoupling will cause ISP failures or transient I/O glitches. Tie all unused VCCIO pins to one of the active VCCIO rails to prevent ESD damage during handling.
Use a 4-layer PCB with a continuous ground plane directly under the TQFP-100 footprint for the MAX II device. Route JTAG signals (TCK, TMS, TDI, TDO) on the top layer with ground guard traces on both sides and keep them under 50 mm total length to avoid programming failures. Group bank-1 and bank-2 I/Os on opposite sides of the package to simplify PCB routing when bridging two voltage domains.
Do not leave any VCCIO bank supply floating - the EPM570GT100C5N has four I/O banks, all of which must be powered even if unused, or the device will fail JTAG IDCODE read. Avoid driving TMS with a slow signal; TCK should be a clean square wave at 10 MHz or below during ISP. The nCEO/nCE pins should be tied high through a 10 kΩ resistor if not used, never left floating - this can cause chain-mode programming to hang.
Place the JTAG header or test pads on the same board edge as the CPLD to keep TCK/TMS trace lengths matched to within 5 mm. Add 33 Ω series damping resistors on TDO when driving long backplane traces to prevent reflections during ISP. The EPM570GT100C5N thermal pad is the bottom of the package body; provide at least 4 thermal vias in a 3x3 array under the device if power dissipation exceeds 0.5 W.
合规信息
RoHS compliant per Intel product page. Commercial temperature grade 0C to +85C only - not AEC-Q100 qualified. Choose MAX V family for AEC-Q100 automotive designs.