EPM570GT100C5N - MAX II CPLD, 570 LEs, 76 I/O, TQFP-100 | Intel
MPN: EPM570GT100C5N ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $18.5 | $18.50 |
| 10 | $16.2 | $162.00 |
| 100 | $14.1 | $1,410.00 |
| 500 | $12.4 | $6,200.00 |
| 1,000 | $11.05 | $11,050.00 |
Drop-in alternatives for EPM570GT100C5N — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EPM570GT100C4N
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View Datasheet →EPM570GT100C3N
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View Datasheet →EPM1270GT100C5N
✅ Drop-In ⚠️ 参数待验证📋 Reference alternative (not in catalog)
EPM240T100C5N
✅ Drop-In ⚠️ 参数待验证✓ In Stock
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View Datasheet →EPM570T100I5N
✅ Drop-In ⚠️ 参数待验证✓ In Stock
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View Datasheet →EPM570GT100C5N Maximum Ratings & Electrical Characteristics
| Series | MAX II |
| Logic Elements | 570 |
| Equivalent Macrocells | 440 |
| User I/O | 76 |
| LABs | 36 |
| Maximum Frequency | 304 MHz |
| User Flash Memory (UFM) | 8 Kbit |
| Operating Supply Voltage (VCCINT) | 2.5 V / 3.3 V |
| I/O Standards Supported | 1.5 V, 1.8 V, 2.5 V, 3.3 V LVTTL/LVCMOS |
| Package | TQFP-100 |
| Mounting Type | Surface Mount |
| Operating Temperature | 0C to +85C (Commercial) |
| Programmability | Flash-based, non-volatile (ISP via JTAG) |
| JTAG Support | IEEE 1149.1 boundary scan |
| RoHS Status | Compliant |
EPM570GT100C5N Pin Configuration
| Pin 1 | I/O — General-purpose user I/O bank 2 |
| Pin 2 | I/O — General-purpose user I/O bank 2 |
| Pin 3 | I/O — General-purpose user I/O bank 2 |
| Pin 4 | I/O — General-purpose user I/O bank 2 |
| Pin 5 | I/O — General-purpose user I/O bank 2 |
| Pin 6 | I/O — General-purpose user I/O bank 2 |
| Pin 7 | I/O — General-purpose user I/O bank 2 |
| Pin 8 | I/O — General-purpose user I/O bank 2 |
| Pin 9 | I/O — General-purpose user I/O bank 2 |
| Pin 10 | I/O — General-purpose user I/O bank 2 |
| Pin 11 | GND — Ground |
| Pin 12 | I/O — General-purpose user I/O bank 2 |
| Pin 13 | I/O — General-purpose user I/O bank 2 |
| Pin 14 | I/O — General-purpose user I/O bank 2 |
| Pin 15 | I/O — General-purpose user I/O bank 2 |
| Pin 16 | I/O — General-purpose user I/O bank 2 |
| Pin 17 | I/O — General-purpose user I/O bank 2 |
| Pin 18 | I/O — General-purpose user I/O bank 2 |
| Pin 19 | I/O — General-purpose user I/O bank 2 |
| Pin 20 | I/O — General-purpose user I/O bank 2 |
| Pin 21 | VCCIO1 — I/O bank 1 supply voltage (1.5/1.8/2.5/3.3 V) |
| Pin 22 | I/O — General-purpose user I/O bank 1 |
| Pin 23 | I/O — General-purpose user I/O bank 1 |
| Pin 24 | I/O — General-purpose user I/O bank 1 |
| Pin 25 | I/O — General-purpose user I/O bank 1 |
| Pin 26 | I/O — General-purpose user I/O bank 1 |
| Pin 27 | I/O — General-purpose user I/O bank 1 |
| Pin 28 | I/O — General-purpose user I/O bank 1 |
| Pin 29 | I/O — General-purpose user I/O bank 1 |
| Pin 30 | I/O — General-purpose user I/O bank 1 |
| Pin 31 | GND — Ground |
| Pin 32 | I/O — General-purpose user I/O bank 1 |
| Pin 33 | I/O — General-purpose user I/O bank 1 |
| Pin 34 | I/O — General-purpose user I/O bank 1 |
| Pin 35 | I/O — General-purpose user I/O bank 1 |
| Pin 36 | I/O — General-purpose user I/O bank 1 |
| Pin 37 | I/O — General-purpose user I/O bank 1 |
| Pin 38 | I/O — General-purpose user I/O bank 1 |
| Pin 39 | I/O — General-purpose user I/O bank 1 |
| Pin 40 | I/O — General-purpose user I/O bank 1 |
| Pin 41 | I/O — General-purpose user I/O bank 1 |
| Pin 42 | VCCINT — Core supply voltage (2.5 V / 3.3 V) |
| Pin 43 | I/O — General-purpose user I/O bank 1 |
| Pin 44 | I/O — General-purpose user I/O bank 1 |
| Pin 45 | I/O — General-purpose user I/O bank 1 |
| Pin 46 | I/O — General-purpose user I/O bank 1 |
| Pin 47 | I/O — General-purpose user I/O bank 1 |
| Pin 48 | I/O — General-purpose user I/O bank 1 |
| Pin 49 | I/O — General-purpose user I/O bank 1 |
| Pin 50 | I/O — General-purpose user I/O bank 1 |
| Pin 51 | GND — Ground |
| Pin 52 | I/O — General-purpose user I/O bank 1 |
| Pin 53 | I/O — General-purpose user I/O bank 1 |
| Pin 54 | I/O — General-purpose user I/O bank 1 |
| Pin 55 | I/O — General-purpose user I/O bank 1 |
| Pin 56 | I/O — General-purpose user I/O bank 1 |
| Pin 57 | I/O — General-purpose user I/O bank 1 |
| Pin 58 | I/O — General-purpose user I/O bank 1 |
| Pin 59 | I/O — General-purpose user I/O bank 1 |
| Pin 60 | I/O — General-purpose user I/O bank 1 |
| Pin 61 | I/O — General-purpose user I/O bank 1 |
| Pin 62 | I/O — General-purpose user I/O bank 1 |
| Pin 63 | VCCIO1 — I/O bank 1 supply voltage (1.5/1.8/2.5/3.3 V) |
| Pin 64 | I/O — General-purpose user I/O bank 1 |
| Pin 65 | I/O — General-purpose user I/O bank 1 |
| Pin 66 | I/O — General-purpose user I/O bank 1 |
| Pin 67 | I/O — General-purpose user I/O bank 1 |
| Pin 68 | I/O — General-purpose user I/O bank 1 |
| Pin 69 | I/O — General-purpose user I/O bank 1 |
| Pin 70 | I/O — General-purpose user I/O bank 1 |
| Pin 71 | GND — Ground |
| Pin 72 | I/O — General-purpose user I/O bank 3 |
| Pin 73 | I/O — General-purpose user I/O bank 3 |
| Pin 74 | I/O — General-purpose user I/O bank 3 |
| Pin 75 | I/O — General-purpose user I/O bank 3 |
| Pin 76 | I/O — General-purpose user I/O bank 3 |
| Pin 77 | I/O — General-purpose user I/O bank 3 |
| Pin 78 | I/O — General-purpose user I/O bank 3 |
| Pin 79 | TDI — JTAG test data input |
| Pin 80 | TCK — JTAG test clock |
| Pin 81 | TMS — JTAG test mode select |
| Pin 82 | VCCINT — Core supply voltage (2.5 V / 3.3 V) |
| Pin 83 | I/O — General-purpose user I/O bank 3 |
| Pin 84 | I/O — General-purpose user I/O bank 3 |
| Pin 85 | I/O — General-purpose user I/O bank 3 |
| Pin 86 | I/O — General-purpose user I/O bank 3 |
| Pin 87 | I/O — General-purpose user I/O bank 3 |
| Pin 88 | I/O — General-purpose user I/O bank 3 |
| Pin 89 | I/O — General-purpose user I/O bank 3 |
| Pin 90 | I/O — General-purpose user I/O bank 3 |
| Pin 91 | GND — Ground |
| Pin 92 | I/O — General-purpose user I/O bank 3 |
| Pin 93 | I/O — General-purpose user I/O bank 3 |
| Pin 94 | I/O — General-purpose user I/O bank 3 |
| Pin 95 | I/O — General-purpose user I/O bank 3 |
| Pin 96 | TDO — JTAG test data output |
| Pin 97 | I/O — General-purpose user I/O bank 4 |
| Pin 98 | I/O — General-purpose user I/O bank 4 |
| Pin 99 | I/O — General-purpose user I/O bank 4 |
| Pin 100 | VCCIO3 — I/O bank 3 supply voltage (1.5/1.8/2.5/3.3 V) |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM570GT100C5N is suitable for 7 applications: Bus Interface Bridging, Power-Up Sequencing Controller, Industrial I/O Expansion, Legacy Glue Logic Replacement, Display & Touch Controller Interface, Automotive Body Electronics (Pre-AEC-Q Era Designs), Medical Device Interface & Isolation Logic.
Bus Interface Bridging
The EPM570GT100C5N excels at bridging mismatched bus protocols - for example, converting a 16-bit 3.3 V parallel bus to a serial SPI link, or gluing an 8-bit legacy 8051 bus to a 32-bit ARM Cortex-M0+ bus at 2.5 V. Its 570 LEs / 440 macrocells accommodate full 16/32-bit address decoding plus handshaking state machines in a single device, while the 304 MHz internal performance ensures zero-wait-state glue for sub-100 MHz buses. The MultiVolt I/O (1.5 V / 1.8 V / 2.5 V / 3.3 V) lets a single EPM570GT100C5N translate between two different voltage domains without external level shifters, saving board space and BOM cost.
Recommended
Power-Up Sequencing Controller
The EPM570GT100C5N's non-volatile flash memory delivers instant-on configuration in less than 1 ms - critical for power-supply sequencing in multi-rail systems such as FPGA+MCU+ADC designs. By the time the upstream DC-DC converters reach regulation, the EPM570 has already asserted enable signals and reset lines in the correct order, eliminating the need for an external supervisor chain. With 76 I/Os, a single device can sequence up to a dozen independent rails, and the 8-Kbit User Flash Memory can store rail-trim calibration constants or fault-log data for diagnostics.
Recommended
Industrial I/O Expansion
Industrial PLCs and motor controllers often run out of GPIO pins - the EPM570GT100C5N adds 76 user I/Os to any microcontroller via SPI, I2C, or parallel bus. Each LE can implement a PWM channel, encoder counter, or simple debouncer; 440 macrocells are sufficient to deploy 32 PWM channels plus 16 quadrature-decoder counters in a single chip. The flash-based ISP allows in-field logic upgrades when a new encoder protocol or motor-control algorithm is required, avoiding the cost of re-spinning the host MCU board.
Recommended
Legacy Glue Logic Replacement
Boards originally built with 74HC/74FTTL glue can be consolidated onto a single EPM570GT100C5N, replacing 20-30 discrete logic packages with one TQFP-100 chip. The 570 LEs cover address decoding, chip-select generation, wait-state insertion, and interrupt prioritization - all at deterministic sub-9 ns pin-to-pin delays. JTAG-based ISP allows the same board to be re-purposed for the next product revision by re-programming the CPLD instead of re-routing traces.
Recommended
Display & Touch Controller Interface
LCD and OLED panels use proprietary interface protocols (RGB-565, LVDS, MIPI-DBI) that microcontrollers often cannot generate natively. The EPM570GT100C5N converts a host MCU's SPI/parallel stream into the exact pixel-clock, sync, and data timing required by the panel, freeing the MCU from bit-banging. The 304 MHz internal performance supports XGA (1024x768) panels, while the MultiVolt I/O interfaces both 1.8 V panel logic and 3.3 V host MCU without level shifters.
Recommended
Automotive Body Electronics (Pre-AEC-Q Era Designs)
Body controllers for window lifts, mirror adjusters, and LED drivers have long used MAX II CPLDs as the multiplexing glue between BCM MCUs and the power-stage drivers. The EPM570GT100C5N's 76 I/Os drive multiple half-bridge FET drivers, implement LIN/CAN message decoding, and run PWM dimming logic simultaneously. For new AEC-Q100 qualified designs, use the automotive-grade Intel MAX V family instead - the EPM570GT100C5N itself is commercial-grade (0C to +85C).
Recommended
Medical Device Interface & Isolation Logic
Patient monitors and diagnostic instruments need deterministic glue logic between sensor front-ends, isolated data converters, and the host processor. The EPM570GT100C5N provides non-volatile instant-on configuration for safety-critical start-up sequences and 76 I/Os to bridge multiple isolated SPI ports. The flash-based design avoids the FPGA-style configuration delay that could miss a critical first-sample window after power-on.
Recommended
Recommended Products Summary
Engineering reference data for EPM570GT100C5N — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM570GT100C4N | EPM570GT100C3N | EPM1270GT100C5N | EPM240T100C5N | EPM570T100I5N |
|---|---|---|---|---|---|---|
| Package | TQFP-100 | TQFP-100 - same | TQFP-100 - same | TQFP-100 - same | TQFP-100 - same | TQFP-100 - same |
| Brand | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) |
| Logic Elements | 570 | 570 (same) | 570 (same) | 1270 (+123%) | 240 (-58%) | 570 (same) |
| Equivalent Macrocells | 440 | 440 (same) | 440 (same) | 980 (+123%) | 192 (-56%) | 440 (same) |
| User I/O | 76 | 76 (same) | 76 (same) | 76 (same) | 76 (same) | 76 (same) |
| Speed Grade | C5 (fastest) | C4 (slower) | C3 (slowest) | C5 (same) | C5 (same) | I5 (industrial) |
| Operating Temperature | 0C to +85C (Commercial) | 0C to +85C (Commercial) | 0C to +85C (Commercial) | 0C to +85C (Commercial) | 0C to +85C (Commercial) | -40C to +100C (Industrial) |
| UFM (User Flash Memory) | 8 Kbit | 8 Kbit (same) | 8 Kbit (same) | 8 Kbit (same) | 8 Kbit (same) | 8 Kbit (same) |
| RoHS | Compliant (lead-free) | Compliant | Compliant | Compliant | Compliant | Compliant |
Key Differentiators
- Highest density in MAX II family available in TQFP-100 (vs EPM240T100C5N)
- Fastest speed grade C5N at 304 MHz (vs EPM570GT100C4N)
- Vertical migration within TQFP-100 (vs EPM1270GT100C5N)
- Non-volatile flash storage with instant-on (vs SRAM-based CPLDs)
Design Notes
Decouple every VCCINT and VCCIO pin with a 0.1 µF X7R ceramic capacitor placed within 3 mm of the corresponding pin, and add one bulk 10 µF tantalum or ceramic cap per bank. The EPM570GT100C5N draws up to 50 mA on VCCINT during in-system programming; insufficient decoupling will cause ISP failures or transient I/O glitches. Tie all unused VCCIO pins to one of the active VCCIO rails to prevent ESD damage during handling.
Use a 4-layer PCB with a continuous ground plane directly under the TQFP-100 footprint for the MAX II device. Route JTAG signals (TCK, TMS, TDI, TDO) on the top layer with ground guard traces on both sides and keep them under 50 mm total length to avoid programming failures. Group bank-1 and bank-2 I/Os on opposite sides of the package to simplify PCB routing when bridging two voltage domains.
Do not leave any VCCIO bank supply floating - the EPM570GT100C5N has four I/O banks, all of which must be powered even if unused, or the device will fail JTAG IDCODE read. Avoid driving TMS with a slow signal; TCK should be a clean square wave at 10 MHz or below during ISP. The nCEO/nCE pins should be tied high through a 10 kΩ resistor if not used, never left floating - this can cause chain-mode programming to hang.
Place the JTAG header or test pads on the same board edge as the CPLD to keep TCK/TMS trace lengths matched to within 5 mm. Add 33 Ω series damping resistors on TDO when driving long backplane traces to prevent reflections during ISP. The EPM570GT100C5N thermal pad is the bottom of the package body; provide at least 4 thermal vias in a 3x3 array under the device if power dissipation exceeds 0.5 W.
Compliance Information
RoHS compliant per Intel product page. Commercial temperature grade 0C to +85C only - not AEC-Q100 qualified. Choose MAX V family for AEC-Q100 automotive designs.
