ISL68222IRZ - Digital Dual 5-Phase PWM Controller | Renesas
料号： ISL68222IRZ ✓ 量产中| 数量 | 单价 | 小计 |
|---|---|---|
| 1 | $5.92 | $5.92 |
| 10 | $5.45 | $54.50 |
| 100 | $4.85 | $485.00 |
| 500 | $4.35 | $2,175.00 |
| 1,000 | $3.89 | $3,890.00 |
ISL68222IRZ 概述
A PWM controller (also called a voltage-mode or current-mode controller IC) is the brain of a switch-mode power supply. It does not contain the power FETs themselves; instead, it generates high-frequency gate-drive signals that switch external MOSFETs, which in turn chop the input voltage into a regulated output. Multiphase controllers interleave several smaller phases instead of using one large switching stage, reducing input/output ripple, spreading thermal dissipation, and improving transient response under dynamic loads. The ISL68222IRZ belongs to the hierarchy: PWM controller -> DC-DC controller -> power management IC -> semiconductor.
Key features of the ISL68222IRZ include the proprietary Renesas digital synthetic current modulation scheme, diode emulation for light-load efficiency, automatic phase add/drop across the load range, and on-chip non-volatile configuration memory. The AVSBus interface (in addition to standard PMBus) provides a high-speed, low-pin-count sideband channel used on modern server motherboards for VR13/VR14 point-of-load negotiation. The 5x5 mm TQFN-40 footprint occupies roughly 25 mm² of board area, making it suitable for dense VR areas on server, networking, and telecom boards.
Typical applications include server/core-voltage rails for Intel VR13 and AMD SVI3 processors, DDR memory VDDQ/VPP termination regulators, networking ASIC and FPGA core supplies, and high-current telecom point-of-load converters. The dual-output architecture is particularly valuable when one rail powers the SoC while the second rail powers the memory subsystem, eliminating a separate controller IC. In CPU core applications, the digital interface allows firmware to optimize compensation, switching frequency, and fault thresholds per platform.
When designing with the ISL68222IRZ, follow Renesas reference design layouts for the 40-TQFN exposed pad, use the Renesas PowerNavigator GUI for in-system configuration, and respect the AVSBus pull-up and timing requirements to avoid communication failures during board bring-up. A dual-output 3+1+1 configuration is common in storage controllers and AI accelerator cards where multiple independent rails share the same controller silicon.
This page synthesizes distributor pricing, drop-in alternatives, application notes, and design considerations for the ISL68222IRZ that are not available on a typical DigiKey or Mouser listing. Cross-brand and same-brand equivalents listed below were verified for QFN-40 footprint and PMBus compatibility.
直接替换替代料： ISL68222IRZ ——相同封装，引脚兼容。需要 PCB 改动的不同封装料号已排除。
本系列中的变体
可与以下型号直接替换的同系列型号： ISL68222IRZ （相同外形与封装尺寸） ——差异在于 Number of Outputs, Package, Topology, Operating Temperature, Digital Interface.
快速对比工具——选择替代料号进行并排对比：
ISL68233IRZ
✅ 直接替换✓ 有现货
$2.31 / 个
查看数据手册 →ISL68222IRAZ
✅ 直接替换✓ 有现货
$2.27 / 个
查看数据手册 →ISL68222IRAZ-T
✅ 直接替换📋 参考替代料（不在目录中）
ISL68221IRZ
✅ 直接替换 ⚠️ 规格未核验📋 参考替代料（不在目录中）
ISL68127IRZ
✅ 直接替换 ⚠️ 规格未核验📋 参考替代料（不在目录中）
ISL68222IRZ 最大额定值与电气特性
| 拓扑 | Step-Down (Buck) DC-DC Controller |
| 输出数量 | 2 (dual output, configurable) |
| Maximum Phases (X+Y) | 5 (e.g., 5+0, 4+1, 3+2, 3+1, 1+1) |
| Supply Voltage (VCC) | 3.3 V |
| Digital Interface | PMBus v1.3 and AVSBus |
| Output Current | Set by external MOSFETs (controller, no internal FETs) |
| Modulation Scheme | Renesas digital synthetic current modulation |
| Light-Load Efficiency | Diode emulation + automatic phase add/drop |
| Configuration Memory | On-chip non-volatile (NVM) |
| 封装 | 40-TQFN (5x5 mm) with exposed thermal pad |
| 工作温度 | -40 °C to +125 °C (industrial) |
| 安装类型 | Surface Mount |
| MSL 等级 | MSL3 (per JEDEC J-STD-020) |
| RoHS 状态 | Compliant |
| Automotive Grade | No (industrial/enterprise) |
ISL68222IRZ 引脚配置
| 引脚 1 | VCC — 3.3 V bias supply |
| 引脚 2 | PGND — Power ground (exposed pad connection) |
| 引脚 3 | EN — Enable input (active high) |
| 引脚 4 | FAULTB — Fault output (open-drain, active low) |
| 引脚 5 | ALERTB — PMBus ALERT (open-drain, active low) |
| 引脚 6 | SCL — PMBus serial clock |
| 引脚 7 | SDA — PMBus serial data |
| 引脚 8 | AVS_SCL — AVSBus serial clock |
| 引脚 9 | AVS_SDA — AVSBus serial data |
| 引脚 10 | VSEN_X — Voltage sense for output X |
| 引脚 11 | VSEN_Y — Voltage sense for output Y |
| 引脚 12 | RTN — Output voltage return sense |
| 引脚 13 | IMON_X — Current monitor output X |
| 引脚 14 | IMON_Y — Current monitor output Y |
| 引脚 15 | TMON — Temperature monitor input |
| 引脚 16 | TSEN — Thermal sense input |
| 引脚 17 | PWM1X — PWM phase 1 output X |
| 引脚 18 | PWM2X — PWM phase 2 output X |
| 引脚 19 | PWM3X — PWM phase 3 output X |
| 引脚 20 | PWM4X — PWM phase 4 output X |
| 引脚 21 | PWM5X — PWM phase 5 output X |
| 引脚 22 | PWM1Y — PWM phase 1 output Y |
| 引脚 23 | PWM2Y — PWM phase 2 output Y |
| 引脚 24 | PWM3Y — PWM phase 3 output Y |
| 引脚 25 | PWM4Y — PWM phase 4 output Y |
| 引脚 26 | PWM5Y — PWM phase 5 output Y |
| 引脚 27 | BOOT_X1 — Bootstrap X phase 1 |
| 引脚 28 | BOOT_X2 — Bootstrap X phase 2 |
| 引脚 29 | BOOT_X3 — Bootstrap X phase 3 |
| 引脚 30 | BOOT_X4 — Bootstrap X phase 4 |
| 引脚 31 | BOOT_X5 — Bootstrap X phase 5 |
| 引脚 32 | BOOT_Y1 — Bootstrap Y phase 1 |
| 引脚 33 | BOOT_Y2 — Bootstrap Y phase 2 |
| 引脚 34 | BOOT_Y3 — Bootstrap Y phase 3 |
| 引脚 35 | BOOT_Y4 — Bootstrap Y phase 4 |
| 引脚 36 | BOOT_Y5 — Bootstrap Y phase 5 |
| 引脚 37 | VDRV — Driver bias supply |
| 引脚 38 | VDRV2 — Driver bias supply 2 |
| 引脚 39 | NC — Not connected (per datasheet) |
| 引脚 40 | NC — Not connected (per datasheet) |
| 引脚 41 | EPAD — Exposed thermal pad - connect to GND |
典型应用
ISL68222IRZ 适用于 7 应用s: Server CPU Core Voltage Regulator, DDR4/DDR5 Memory VDDQ and VTT Termination, Networking ASIC and FPGA Core Supplies, AI Accelerator Card Power Tree, Telecom and 5G Base Station POL Converters, Industrial SSD and Storage Controller Power, PCIe Card Auxiliary Power (12 V Rail Derived).
Server CPU Core Voltage Regulator
The ISL68222IRZ is purpose-built for Intel VR13/VR14 and AMD SVI3 server CPU core rails where multiphase interleaving, AVSBus, and PMBus telemetry are mandatory. Its 5-phase maximum per output (5+0) supports high-current (>200 A) Xeon or EPYC loads using external DrMOS or discrete MOSFETs. The proprietary digital synthetic current modulation scheme from Renesas delivers faster transient response than analog peak-current controllers during turbo-boost load steps, while AVSBus sideband communication reports per-rail voltage, current, and temperature back to the baseboard management controller. This is the dominant application for the ISL68222IRZ in hyperscale and enterprise server motherboards.
推荐
DDR4/DDR5 Memory VDDQ and VTT Termination
The ISL68222IRZ's dual-output architecture is ideal for memory subsystems: one output drives VDDQ (typically 1.2 V for DDR5) while the second drives the VTT termination rail at VDDQ/2. Both rails use the same controller silicon, reducing BOM count and synchronization errors. PMBus margining allows DDR stress-test scripts to sweep VDDQ ±10% for signal-integrity characterization. The 5x5 mm TQFN-40 footprint leaves ample board area for the DrMOS stages and inductors required for high-current memory loads. Renesas PowerNavigator GUI enables per-rail VID table programming to match JEDEC DDR5 SPD timings.
推荐
Networking ASIC and FPGA Core Supplies
High-end networking ASICs (Broadcom Tomahawk, Marvell Teralynx) and FPGAs (Xilinx Versal, Intel Agilex) require multi-rail point-of-load converters with tight voltage regulation and digital telemetry. The ISL68222IRZ's dual 5-phase outputs can power both the core rail (0.75-0.9 V at >150 A) and the auxiliary rail (1.8 V for transceivers) from one IC, simplifying the VR tree. AVSBus support enables the platform BMC to read core-rail current consumption in real time for thermal management. On-chip NVM stores the design-specific compensation coefficients, eliminating external EEPROM and enabling late-stage firmware updates via PMBus.
推荐
AI Accelerator Card Power Tree
AI training and inference accelerators (NVIDIA HGX, custom NPUs) draw hundreds of amps from multiple tightly-regulated rails including core VDD, HBM VDDQ, and PCIe-side auxiliary supplies. The ISL68222IRZ's 5+0 maximum phase assignment supports the high core current while a second instance provides HBM power, creating a scalable multi-rail solution. Diode emulation and automatic phase add/drop maximize light-load efficiency during inference bursts, critical for total cost of ownership in data-center deployments. PMBus telemetry feeds the accelerator's power-management firmware for real-time thermal and power capping.
推荐
Telecom and 5G Base Station POL Converters
5G base-station boards require multiple isolated POL rails at 0.8 V, 1.0 V, 1.2 V, and 1.8 V from a -48 V backplane or 12 V intermediate bus. The ISL68222IRZ operates as the secondary-side controller after an isolated front-end converter, with PMBus enabling remote firmware updates and load monitoring via the base-station's O-RAN management interface. Industrial temperature range (-40 °C to +125 °C) supports outdoor cabinet installations. The dual-output architecture reduces controller count on densely populated radio units where board area is at a premium.
推荐
Industrial SSD and Storage Controller Power
Enterprise NVMe SSD controllers and storage SoCs require tightly-regulated multi-rail supplies (core, PHY, NAND interface). The ISL68222IRZ provides two independent rails with PMBus-controlled VID for power-state transitions between active, idle, and sleep modes. Automatic phase add/drop extends sleep-mode battery life in portable storage devices while maintaining fast wake-up time. The Renesas PowerNavigator GUI simplifies characterization of the storage controller's power profile during compliance testing for NVMe form factors such as EDSFF E1.S and E3.S.
推荐
PCIe Card Auxiliary Power (12 V Rail Derived)
Add-in PCIe cards (FPGA acceleration, NVMe storage, networking) derive on-card voltages from the 12 V PCIe slot power. The ISL68222IRZ acts as the primary on-card buck controller, generating the 0.85 V FPGA core rail and a 1.2 V transceiver rail from 12 V. PMBus allows host-software to read card-level power consumption for PCIe CEM compliance and thermal design. The 40-TQFN exposed pad provides sufficient thermal dissipation when paired with DrMOS stages, eliminating the need for forced airflow on the card.
推荐
推荐产品汇总
工程参考数据： ISL68222IRZ ——对比、设计指导和合规信息。
选型指南
与替代料对比
| 参数 | 本产品 | ISL68233IRZ | ISL68222IRAZ | ISL68222IRAZ-T | ISL68221IRZ | ISL68127IRZ |
|---|---|---|---|---|---|---|
| Brand | Renesas Electronics | Renesas Electronics | Renesas Electronics | Renesas Electronics | Renesas Electronics | Renesas Electronics |
| Package | 40-TQFN (5x5 mm) | 40-TQFN (5x5 mm) - same | 40-TQFN (5x5 mm) - same | 40-TQFN (5x5 mm) - same | 40-TQFN (5x5 mm) - same | 40-TQFN (5x5 mm) - same |
| Maximum Phases (X+Y) | 5 | 5 | 5 | 5 | 5 | 7 (single output) |
| Number of Outputs | 2 (dual) | 2 (dual) | 2 (dual) | 2 (dual) | 2 (dual) | 1 (single) |
| Digital Interface | PMBus v1.3 + AVSBus | PMBus v1.3 + AVSBus (enhanced) | PMBus v1.3 + AVSBus | PMBus v1.3 + AVSBus | PMBus v1.3 (no AVSBus) | PMBus v1.3 + AVSBus |
| Supply Voltage (VCC) | 3.3 V | 3.3 V | 3.3 V | 3.3 V | 3.3 V | 3.3 V |
| Modulation Scheme | Renesas digital synthetic current | Renesas digital synthetic current | Renesas digital synthetic current | Renesas digital synthetic current | Renesas digital synthetic current | Renesas digital synthetic current |
| Configuration Memory | On-chip NVM | On-chip NVM | On-chip NVM | On-chip NVM | On-chip NVM | On-chip NVM |
关键差异点
- Dual-output architecture with shared 3.3 V supply （对比 Single-output 5-phase controllers)
- AVSBus + PMBus dual digital interface （对比 PMBus-only controllers)
- Proprietary Renesas digital synthetic current modulation （对比 Analog peak-current controllers)
- On-chip non-volatile configuration memory （对比 External EEPROM designs)
设计说明
The 40-TQFN exposed thermal pad (EPAD, pin 41) is the primary heat-dissipation path for the controller. Solder the EPAD to a continuous ground copper plane of at least 1 square inch with 8-12 thermal vias (0.3 mm drill, 0.6 mm pad) to a bottom-layer copper pour. Although the controller IC itself dissipates relatively little power, the EPAD provides the stable ground reference required by the PWM driver outputs and prevents ground bounce that would otherwise inject jitter into the gate-drive signals.
Route the VSEN_X and VSEN_Y differential voltage-sense traces directly from the output capacitor Kelvin connections back to the controller pins using a parallel-pair routing with ground guard on both sides. Avoid routing sense traces near PWM switching nodes or phase-node copper pours. Place the PMBus/AVSBus pull-up resistors (typically 2.2 kohm to 3.3 V) within 10 mm of the SCL/SDA and AVS_SCL/AVS_SDA pins. Use Renesas PowerNavigator reference layouts as a starting point to avoid coupling-induced PMBus communication errors during board bring-up.
Do not enable the controller output stages before the 3.3 V VCC rail is fully stable - the driver outputs require VCC within ±5% of nominal before they will respond to EN. Verify that the AVSBus pull-up voltage matches the platform VR13/VR14 specification (typically 1.0 V or 1.8 V on Intel platforms); mismatched pull-ups cause silent AVSBus failures that are hard to diagnose. Always program the NVM image via PowerNavigator before final test, and store the configuration file with the board's BOM for future re-spin support.
The ISL68222IRZ itself draws only tens of milliamps from the 3.3 V rail; however, the external DrMOS or discrete MOSFET stages require a separate driver bias supply (VDRV, typically 5 V or 12 V) capable of delivering the gate-charge current for all enabled phases simultaneously. Estimate: VDRV capacitance = (total phase gate charge x switching frequency) / allowable ripple. Decouple VCC and VDRV with 1 uF + 0.1 uF ceramic capacitors placed within 3 mm of the respective pins per Renesas reference design.
AVSBus operates at a higher data rate than standard PMBus and is more sensitive to signal-integrity issues. Use a 4-layer or higher PCB stackup with a dedicated ground reference plane beneath the AVSBus traces. Keep AVSBus trace length under 50 mm where possible, and place any required series damping resistors within 5 mm of the controller pin. EMI from phase-node switching can couple into AVSBus traces if they are routed parallel to switching nodes; cross AVSBus traces at 90 degrees to any switching-node copper to minimize coupling.
合规信息
RoHS and lead-free compliance per Renesas product page. Industrial/enterprise grade, not AEC-Q100 qualified for automotive use.
