LMR33630CDDAR - 3A Synchronous Buck Converter, 36V | TI
料号： LMR33630CDDAR ✓ 量产中| 数量 | 单价 | 小计 |
|---|---|---|
| 1 | $3.45 | $3.45 |
| 10 | $3.1 | $31.00 |
| 100 | $2.65 | $265.00 |
| 500 | $2.25 | $1,125.00 |
| 1,000 | $1.95 | $1,950.00 |
LMR33630CDDAR 概述
What is a synchronous buck converter? A buck converter (step-down switching regulator) is a switched-mode power supply topology that steps a higher DC input voltage down to a lower DC output voltage. A synchronous buck replaces the rectifier diode with a low-side MOSFET to reduce conduction losses, achieving >90% efficiency. The LMR33630 belongs to the SIMPLE SWITCHER family -> switching regulator -> DC/DC converter -> power management IC -> semiconductor, optimized for rugged industrial environments.
Key features include a wide 3.8 V to 36 V operating input range, an adjustable output from 1 V to 24 V (per the Xecor comparison data), 24 uA quiescent current, internal compensation that eliminates external loop components, and a power-good flag output for sequencing. The 2.1 MHz switching frequency enables a small inductor and ceramic output capacitors, shrinking total solution size. Ultra-low EMI design reduces input filter complexity.
The LMR33630 uses peak-current-mode control with an internal compensation network, allowing closed-loop stability with ceramic output capacitors without ESR compensation. Its 30 ns minimum on-time supports large step-down ratios, while the 8-pin HSOIC EP package with an exposed thermal pad keeps junction temperature low at full 3 A load even at elevated ambient.
Typical applications include industrial 24 V rails, factory automation sensors, battery-powered portable equipment, point-of-load regulation from 12 V/24 V buses, and low-noise analog supply post-regulation.
When designing, place the input ceramic capacitor directly across PVIN and PGND within 2 mm of the package, use a low-DCR shielded inductor, and follow TI's recommended 4-layer PCB layout to meet EMI margins.
This page consolidates distributor pricing, drop-in alternatives, and engineering design notes synthesized from the LMR33630 datasheet, complementing the manufacturer datasheet with selection and cross-reference guidance.
直接替换替代料： LMR33630CDDAR ——相同封装，引脚兼容。需要 PCB 改动的不同封装料号已排除。
本系列中的变体
可与以下型号直接替换的同系列型号： LMR33630CDDAR （相同外形与封装尺寸） ——差异在于 Control Mode, MSL Level, Output Voltage Range, Package, Power-Good Flag.
快速对比工具——选择替代料号进行并排对比：
LMR33630CDDA
✅ 直接替换📋 参考替代料（不在目录中）
LMR33640ADDAR
✅ 直接替换✓ 有现货
$2.18 / 个
查看数据手册 →LMR33630ADDA
✅ 直接替换📋 参考替代料（不在目录中）
LMR33630BRNXT
✅ 直接替换📋 参考替代料（不在目录中）
LM73605
✅ 直接替换📋 参考替代料（不在目录中）
LMR33630CDDAR 最大额定值与电气特性
| 拓扑 | Synchronous Step-Down (Buck) |
| 输入电压范围 | 3.8 V to 36 V |
| 输出电压范围 | 1 V to 24 V |
| 最大输出电流 | 3 A |
| 开关频率 | 2.1 MHz (DDA grade) |
| Switching Frequency Range | 400 kHz to 2.1 MHz |
| Quiescent Current (typ) | 24 uA |
| Control Mode | Peak Current Mode with internal compensation |
| 效率 | Up to >90% (load and VIN-dependent) |
| 封装 | 8-pin HSOIC EP (DDA) PowerPAD |
| 安装类型 | Surface Mount |
| 工作温度范围 | -40 C to +125 C (TJ) |
| MSL 等级 | Level-2, 260 C, 1 year |
| Power-Good Flag | Yes |
| EMI | Ultra-low EMI design |
| RoHS 状态 | Compliant |
LMR33630CDDAR 引脚配置
| 引脚 1 | EN/UVLO — Enable and undervoltage lockout threshold input |
| 引脚 2 | PGND — Power ground return for low-side FET |
| 引脚 3 | PVIN — Power input voltage supply |
| 引脚 4 | PVIN — Power input voltage supply (tied to pin 3) |
| 引脚 5 | SW — Switching node - connection to inductor |
| 引脚 6 | SW — Switching node - connection to inductor (tied to pin 5) |
| 引脚 7 | PGND — Power ground return |
| 引脚 8 | PGOOD/FB — Power-good indicator and feedback |
典型应用
LMR33630CDDAR 适用于 6 应用s: Industrial 24 V Bus Point-of-Load Regulation, Factory Automation Sensor Power, Battery-Powered Portable Equipment, 12 V/24 V Distributed Power Post-Regulation, Low-Noise Analog Supply Post-Regulation, Ruggedized IoT Edge Gateways.
Industrial 24 V Bus Point-of-Load Regulation
The LMR33630CDDAR is purpose-built for 24 V industrial bus rails thanks to its 3.8 V to 36 V input range and ultra-low EMI design. It converts 24 V nominal down to 3.3 V or 5 V logic rails for PLCs, sensors, and motor drivers, tolerating load-dump transients and cold-crank dips. The 2.1 MHz switching frequency shrinks the input/output filter, and 24 uA quiescent current supports sleep-mode operation. In a typical 24 V application the LMR33630CDDAR delivers 3 A at 5 VOUT with >92% efficiency, leaving margin for upstream protection. Compared to discrete buck designs, the internal compensation eliminates the COMP pin loop network, reducing BOM count by 4-6 components.
推荐
Factory Automation Sensor Power
Factory automation sensors (pressure, flow, proximity, IO-Link) require tightly regulated low-voltage rails from a 24 V backplane. The LMR33630CDDAR's 24 uA quiescent current and 3 A capacity support sensor clusters with both idle and active modes. Its power-good flag enables MCU-driven rail sequencing, while the 8-pin HSOIC EP package with PowerPAD dissipates full 3 A at 24 V to 5 V without a heatsink. Ultra-low EMI simplifies EN 55011/CISPR 11 compliance for industrial sensor modules. The internal compensation supports ceramic-only output capacitance (POSCAP, X7R), reducing long-term drift from capacitor aging in factory environments.
推荐
Battery-Powered Portable Equipment
For battery-powered portable systems, the LMR33630CDDAR's 24 uA quiescent current extends standby time by an order of magnitude versus discrete buck regulators. The wide 3.8 V to 36 V input accommodates multi-cell Li-ion (8.4 V max) and 12 V adapter charging inputs. At 3 A continuous output, the device powers displays, RF transceivers, and MCU cores from a single regulator. The 2.1 MHz switching frequency pushes ripple above AM band (>1.8 MHz), minimizing audio-frequency interference. PFM-mode operation at light load maintains >80% efficiency across the 100 mA to 3 A range, critical for handheld and wearable devices.
推荐
12 V/24 V Distributed Power Post-Regulation
Distributed power architectures use a single 12 V or 24 V intermediate bus with local point-of-load regulators delivering 1 V to 5 V rails. The LMR33630CDDAR excels in this role: its 36 V input tolerance withstands transient overshoot on long 24 V harnesses, while the 3 A output powers FPGAs, SoCs, and analog front-ends. The internal compensation eliminates complex Type-III loops typical of externally-compensated POLs, enabling fast design cycles. Power-good flag supports multi-rail sequencing demanded by modern processors that require core-rail-before-I/O-rail startup. The 8-pin HSOIC EP package allows single-sided assembly, reducing manufacturing cost.
推荐
Low-Noise Analog Supply Post-Regulation
After a switching pre-regulator supplies a noisy intermediate bus, a low-noise linear post-regulator typically powers precision analog circuits. However, a high-frequency synchronous buck like the LMR33630CDDAR can directly power analog rails when its 2.1 MHz fundamental is well-filtered; with adequate LC filtering the output ripple falls below 10 mV pk-pk, suitable for 12-16 bit ADC reference rails. The ultra-low EMI design minimizes conducted emissions that couple into adjacent analog traces. With 24 uA quiescent current, the regulator adds little idle drain to the analog subsystem. Designers pair the LMR33630CDDAR with an LDO (e.g. TPS7A47) when sub-mV ripple is required.
推荐
Ruggedized IoT Edge Gateways
Edge IoT gateways deployed in industrial environments need wide-VIN tolerance, EMI immunity, and small footprint. The LMR33630CDDAR's 3.8 V to 36 V input tolerates long 24 V cabling with motor-noise transients, while ultra-low EMI simplifies CE/FCC compliance at the gateway enclosure. The 3 A output powers a Linux-class SoC, Wi-Fi/LoRa radio, and auxiliary sensors simultaneously. The internal compensation and PowerPAD package enable a single-sided 2-layer PCB, reducing gateway BOM cost by 30% versus 4-layer designs. The 24 uA quiescent supports deep-sleep power profiles under 100 uA system-level.
推荐
推荐产品汇总
工程参考数据： LMR33630CDDAR ——对比、设计指导和合规信息。
选型指南
与替代料对比
| 参数 | 本产品 | LMR33630CDDA | LMR33640ADDAR | LMR33630ADDA | LMR33630BRNXT | LM73605 |
|---|---|---|---|---|---|---|
| Package | 8-pin HSOIC EP (DDA) PowerPAD | 8-pin HSOIC EP (DDA) PowerPAD - same | 8-pin HSOIC EP (DDA) PowerPAD - same | 8-pin HSOIC EP (DDA) PowerPAD - same | 8-pin WSON (BRNX) - different footprint | 8-pin WSON - different footprint |
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| Output Current | 3 A | 3 A | 4 A | 3 A | 3 A | 5 A |
| Input Voltage Range | 3.8 V to 36 V | 3.8 V to 36 V | 3.8 V to 36 V | 3.8 V to 36 V | 3.8 V to 36 V | 3.5 V to 36 V |
| Output Voltage Range | 1 V to 24 V | 1 V to 24 V | 1 V to 24 V | 1 V to 24 V | 1 V to 24 V | 1 V to 20 V |
| Power-Good Flag | Yes | Yes | Yes | Yes | Yes | Yes |
| Internal Compensation | Yes | Yes | Yes | Yes | Yes | Yes |
关键差异点
- Highest switching frequency in 3 A 36 V family （对比 LMR33630CDDA)
- Drop-in 4 A upgrade path in same footprint （对比 LMR33640ADDAR)
- Ultra-low quiescent current for sleep-mode efficiency （对比 LM73605)
- TI SIMPLE SWITCHER ecosystem and internal compensation （对比 LMR33630ADDA)
设计说明
Place a 2.2 uF X7R ceramic input capacitor (CIN) within 2 mm of the PVIN and PGND pins to minimize switching-node parasitic inductance and ringing. Use wide copper pours for PVIN, PGND, and SW to handle 3 A continuous current. The PowerPAD must be soldered to a top-side copper island with at least 8 thermal vias to the inner ground plane for heatsinking. Per the TI datasheet, a 4-layer PCB with dedicated ground plane is recommended for EMI performance.
At VIN = 24 V and VOUT = 5 V delivering 3 A, the LMR33630CDDAR dissipates approximately (24 - 5) * 3 * (1 - efficiency) = ~5 W in worst case (assume 85% efficiency, so ~7 W internal). The 8-pin HSOIC EP package has a theta_JA around 40 C/W with proper PowerPAD layout, giving a 200 C junction rise - above the 125 C limit. Derate input voltage, add airflow, or move to the 4 A LMR33640ADDAR with heatsinking. Always validate thermals at maximum VIN and full load in system characterization.
Do not omit the bootstrap capacitor (CBOOT, typically 0.1 uF) between BOOT and SW pins - without it the high-side FET loses gate drive and the regulator fails to start. Ensure EN/UVLO is not left floating; tie to VIN via a 100 kohm resistor for default-on operation. Do not operate below 3.8 V minimum input - the undervoltage lockout will disable the regulator. Do not exceed 36 V input - load-dump and inductive transients can destroy the device; add a TVS or input clamp if the application sees 24 V load-dump pulses above 36 V.
The LMR33630CDDAR features ultra-low EMI design, but to meet EN 55011/CISPR 11 Class B in industrial applications, add a small LC pi-filter (10 uH inductor + 4.7 uF X7R) on PVIN. Keep SW node copper area minimal to reduce antenna-mode radiation. Place sensitive analog traces and signal planes away from the SW node and inductor; the SW node is a 30+ V pk-pk square wave at 2.1 MHz with strong harmonics.
Inductor selection: choose a shielded power inductor with saturation current >4 A and DCR <30 mOhm for >90% efficiency at 3 A. Output capacitance: a 22 uF X7R ceramic per phase or 2x22 uF in parallel keeps output ripple below 30 mV pk-pk at 5 VOUT. Add a feedforward capacitor (CFF, 22 pF typical) across the upper feedback resistor to improve transient response by 30% per the TI datasheet.
合规信息
RoHS compliant per PartGenie. Not AEC-Q100 qualified; choose automotive-grade variants (LMR33630-Q1) for automotive. MSL Level-2, 260 C, 1 year floor life.
