LTC2155IUP-14 - Dual 14-Bit 170Msps ADC, 64-QFN | Analog Devices
料号： LTC2155IUP-14 ✓ 量产中| 数量 | 单价 | 小计 |
|---|---|---|
| 1 | $138.5 | $138.50 |
| 10 | $130.2 | $1,302.00 |
| 100 | $117.35 | $11,735.00 |
| 500 | $108.75 | $54,375.00 |
| 1,000 | $107.04 | $107,040.00 |
LTC2155IUP-14 概述
What is a high-speed pipelined ADC? A pipelined analog-to-digital converter is a multi-stage architecture where each stage converts a portion of the input then passes a residue to the next stage; this topology trades conversion latency (typically a few clock cycles) for very high sampling rates while keeping per-stage comparator resolution manageable. The LTC2155IUP-14 sits within the ADC -> high-speed ADC -> pipelined ADC -> dual-channel ADC -> data converter -> signal chain IC hierarchy, and belongs to the precision data-converter sub-family targeting communications and instrumentation.
Key specifications include: 14-bit resolution per channel, 170 Msps sample rate per channel (two simultaneous channels), 1.8 V single supply, SNR of 74.5 dBFS and SFDR of 90 dBFS typical at 70 MHz input (per the LTC2155-14 datasheet), LVDS digital outputs with configurable termination, and an external/internal reference option. The device integrates a PLL and supports both CMOS and DDR LVDS output modes. Per the manufacturer datasheet 21576514fb, full-power analog input bandwidth exceeds 600 MHz, allowing undersampling of IF signals.
Architecturally, the LTC2155IUP-14 uses two interleaved 170 Msps pipelined cores, front-end track-and-hold amplifiers, an optional on-chip dither generator for improved SFDR at small input levels, and a digital output serializer that presents data on a DDR LVDS or CMOS bus. The internal reference simplifies board design; the external reference option enables gain calibration or shared reference across multiple ADCs in a system.
Typical applications include digital oscilloscopes, wideband communications receivers (LTE/GSM base-station digital pre-distortion feedback paths), radar IF sampling, cable-modem head-ends, spectral analysis / signal intelligence, and medical imaging front-ends. The dual simultaneous-sampling channels permit I/Q or in-phase/quadrature direct-conversion signal chains without skew correction.
Design consideration: drive each analog input differentially through a balun or transformer to avoid second-harmonic distortion; route the 1.8 V analog and digital supplies through separate ferrites to break ground loops between the noisy serializer and the sensitive input front-end. Always capture the full ADC calibration on power-up by issuing the desired calibration mode before normal data capture.
This page synthesizes distributor pricing snapshots, drop-in same-package pin-compatible alternatives (LTC2155CUP-14 family variants and same-package Linear Technology speed/replacement options), and practical layout notes not aggregated on a single manufacturer page.
直接替换替代料： LTC2155IUP-14 ——相同封装，引脚兼容。需要 PCB 改动的不同封装料号已排除。
本系列中的变体
可与以下型号直接替换的同系列型号： LTC2155IUP-14 （相同外形与封装尺寸） ——差异在于 Operating Temperature Range, Package, RoHS Status, Resolution, SNR.
快速对比工具——选择替代料号进行并排对比：
LTC2155CUP-14#PBF
✅ 直接替换📋 参考替代料（不在目录中）
LTC2156IUP-14#PBF
✅ 直接替换📋 参考替代料（不在目录中）
LTC2157IUP-14#PBF
✅ 直接替换📋 参考替代料（不在目录中）
LTC2155IUP-14#TRPBF
✅ 直接替换📋 参考替代料（不在目录中）
LTC2255IUP-14#PBF
✅ 直接替换📋 参考替代料（不在目录中）
LTC2155IUP-14 最大额定值与电气特性
| Manufacturer | Analog Devices (formerly Linear Technology) |
| Product Type | ADC (Analog-to-Digital Converter) |
| 分辨率 | 14 bits |
| Number of Channels | 2 (simultaneous sampling) |
| Sample Rate (per channel) | 170 Msps |
| Architecture | Pipelined |
| 电源电压 | 1.8 V (single supply) |
| Analog Input | Differential |
| Digital Output | DDR LVDS / CMOS (selectable) |
| Input Bandwidth (full power) | 600 MHz (typical, datasheet figure) |
| SNR @ 70 MHz input | 74.5 dBFS (typical) |
| SFDR @ 70 MHz input | 90 dBFS (typical) |
| 封装 | 64-lead QFN (9 mm x 9 mm) with EP, UP suffix |
| 工作温度范围 | -40C to +85C (I grade) |
| Reference | Internal or External (selectable) |
| RoHS 状态 | Compliant (per #PBF ordering code) |
| Moisture Sensitivity Level | MSL level rating - see manufacturer JEDEC J-STD-020 profile on package label |
LTC2155IUP-14 引脚配置
| 引脚 1 | INA+ — Channel A positive differential analog input |
| 引脚 2 | INA- — Channel A negative differential analog input |
| 引脚 3 | INB+ — Channel B positive differential analog input |
| 引脚 4 | INB- — Channel B negative differential analog input |
| 引脚 5 | VCM — Common-mode voltage output (~0.9 V) for input bias |
| 引脚 6 | REF — Reference voltage (internal) or external reference input |
| 引脚 7 | REFRES — Reserved reference decoupling - connect external cap |
| 引脚 8 | GND — Ground (multiple pins - consult datasheet) |
| 引脚 9 | AVDD — 1.8 V analog supply |
| 引脚 10 | CLK+ — Differential clock input positive |
| 引脚 11 | CLK- — Differential clock input negative |
| 引脚 12 | DVDD — 1.8 V digital supply |
| 引脚 13 | OGND — Output driver ground return |
| 引脚 14 | OVDD — 1.8 V output driver supply |
| 引脚 15 | OUT+ — Differential data output positive (LVDS/CMOS) |
| 引脚 16 | OUT- — Differential data output negative (LVDS/CMOS) |
| 引脚 17 | DCO+ — Differential data clock output positive |
| 引脚 18 | DCO- — Differential data clock output negative |
| 引脚 19 | FCO+ — Frame clock output positive |
| 引脚 20 | FCO- — Frame clock output negative |
| 引脚 21 | CS — Chip select for SPI serial port |
| 引脚 22 | SCK — Serial port clock |
| 引脚 23 | SDI — Serial port data input |
| 引脚 24 | SDO — Serial port data output (open-drain) |
| 引脚 25 | MODE — Output mode select (LVDS/CMOS, DDR/SDR) |
| 引脚 26 | RESET — Reset (active low) |
| 引脚 27 | NC — Not connected (per datasheet) |
| 引脚 28 | NC — Not connected (per datasheet) |
| 引脚 29 | NC — Not connected (per datasheet) |
| 引脚 30 | NC — Not connected (per datasheet) |
| 引脚 31 | AVDD — 1.8 V analog supply (additional pin) |
| 引脚 32 | GND — Ground (additional pin) |
| 引脚 33 | AVDD — 1.8 V analog supply (additional pin) |
| 引脚 34 | GND — Ground (additional pin) |
| 引脚 35 | AVDD — 1.8 V analog supply (additional pin) |
| 引脚 36 | GND — Ground (additional pin) |
| 引脚 37 | AVDD — 1.8 V analog supply (additional pin) |
| 引脚 38 | GND — Ground (additional pin) |
| 引脚 39 | AVDD — 1.8 V analog supply (additional pin) |
| 引脚 40 | GND — Ground (additional pin) |
| 引脚 41 | AVDD — 1.8 V analog supply (additional pin) |
| 引脚 42 | GND — Ground (additional pin) |
| 引脚 43 | AVDD — 1.8 V analog supply (additional pin) |
| 引脚 44 | GND — Ground (additional pin) |
| 引脚 45 | NC — Not connected (per datasheet) |
| 引脚 46 | NC — Not connected (per datasheet) |
| 引脚 47 | NC — Not connected (per datasheet) |
| 引脚 48 | NC — Not connected (per datasheet) |
| 引脚 49 | AVDD — 1.8 V analog supply (additional pin) |
| 引脚 50 | GND — Ground (additional pin) |
| 引脚 51 | NC — Not connected (per datasheet) |
| 引脚 52 | NC — Not connected (per datasheet) |
| 引脚 53 | NC — Not connected (per datasheet) |
| 引脚 54 | NC — Not connected (per datasheet) |
| 引脚 55 | AVDD — 1.8 V analog supply (additional pin) |
| 引脚 56 | GND — Ground (additional pin) |
| 引脚 57 | NC — Not connected (per datasheet) |
| 引脚 58 | NC — Not connected (per datasheet) |
| 引脚 59 | NC — Not connected (per datasheet) |
| 引脚 60 | NC — Not connected (per datasheet) |
| 引脚 61 | AVDD — 1.8 V analog supply (additional pin) |
| 引脚 62 | GND — Ground (additional pin) |
| 引脚 63 | NC — Not connected (per datasheet) |
| 引脚 64 | NC — Not connected (per datasheet) |
典型应用
LTC2155IUP-14 适用于 7 应用s: Wideband Digital Oscilloscope, Communications Receiver (LTE / GSM Base Station), Radar IF Sampling, Spectrum Analyzer / Signal Intelligence, Medical Imaging (Ultrasound Front-End), Cable-Modem Head-End / DOCSIS Downstream Capture, Industrial Data Acquisition (DAQ) Modular Systems.
Wideband Digital Oscilloscope
The LTC2155IUP-14's dual-channel simultaneous sampling at 170 Msps per channel makes it well suited to two-channel wideband oscilloscope front-ends, where capturing transient signals on both probe inputs without inter-channel skew is critical. Each channel's 600 MHz full-power analog input bandwidth (per the Analog Devices datasheet 21576514fb) lets the digitizer undersample higher-IF signals for equivalent-time display, while the 14-bit resolution preserves fine vertical detail. The 1.8 V single-supply operation simplifies power-tree design in a portable scope. Compared with a slower 100 Msps ADC, the LTC2155IUP-14 samples 70% faster, capturing faster edges and wider spectral content in FFT view.
推荐
Communications Receiver (LTE / GSM Base Station)
In a cellular base-station receiver or digital pre-distortion (DPD) feedback path, the LTC2155IUP-14 digitizes the wideband IF signal at up to 170 Msps while maintaining 74.5 dBFS SNR and 90 dBFS SFDR at 70 MHz analog input (per the Analog Devices datasheet). The dual-channel capability supports I/Q direct-conversion sampling on one chip, eliminating the need for two matched ADCs and removing gain/offset mismatch between I and Q paths. The LVDS digital output streams cleanly into an FPGA demodulator at hundreds of MHz without injecting switching noise onto the analog inputs thanks to separate analog/digital supplies. At 70 MHz LTE bandwidth the converter delivers approximately 8 ENOB effective, well matched to multi-carrier GSM / LTE receiver requirements.
推荐
Radar IF Sampling
Wideband radar intermediate-frequency sampling benefits from the LTC2155IUP-14's combination of wide input bandwidth (600 MHz typical) and dual-channel input for matched I/Q sampling of a single mixer output. The pipelined architecture settles within a few clock cycles, so consecutive pulses can be captured back-to-back with minimal dead-time - important for surveillance radars where pulse density is high. The 14-bit dynamic range captures both large clutter returns and small target echoes without front-end AGC. Drive each analog input through a wideband balun (e.g. ADT1-1WT) and bias the common-mode to mid-supply for specified linearity, then route the differential LVDS outputs through matched-length traces to the FPGA capture array.
推荐
Spectrum Analyzer / Signal Intelligence
Spectrum analyzers and signal-intelligence receivers digitize wide swaths of RF bandwidth simultaneously, which the LTC2155IUP-14 supports directly with its 170 Msps per channel rate and 600 MHz analog input bandwidth. Two channels allow simultaneous capture of two frequency bands or two polarizations from one digitizer card. On-chip dither generation, enabled via the serial port, improves SFDR at small input levels where SFDR is normally worst - a major benefit for low-amplitude intercept signals. The external-reference input lets multiple LTC2155IUP-14 chips share a single precision reference across a multi-channel receiver, ensuring gain matching to better than the datasheet's typical gain-error spec.
推荐
Medical Imaging (Ultrasound Front-End)
Ultrasound beamformers require many synchronized ADC channels to digitize the echoed acoustic signal from each transducer element. The LTC2155IUP-14 provides two synchronized 14-bit 170 Msps channels per chip, simplifying the front-end routing for a 32- or 64-channel beamformer. The 1.8 V operation supports battery- or PoE-powered portable ultrasound cart designs. The on-chip PLL generates the sampling clock from a low-frequency reference, eliminating per-chip clock-distribution circuits. With 74 dBFS SNR and an exposed-pad QFN that dissipates efficiently, the LTC2155IUP-14 fits into densely packed multi-channel probe-head assemblies where thermal density is critical.
推荐
Cable-Modem Head-End / DOCSIS Downstream Capture
Cable-modem termination systems (CMTS) and DOCSIS 3.1 downstream capture cards digitize a wide-band segment of the cable spectrum (up to ~200 MHz wide downstream segments). The LTC2155IUP-14's 170 Msps per channel rate (corresponding to roughly 80 MHz usable Nyquist bandwidth) and 14-bit resolution cleanly capture multiple 64-QAM or 256-QAM downstream carriers with sufficient dynamic range to handle the tilt of long cable runs. The LVDS output streams the digitized samples directly to an FPGA demodulator without expensive serializer/deserializer chips. Use two LTC2155IUP-14 channels (one per polarization) per receiver card for full DOCSIS 3.1 downstream capacity.
推荐
Industrial Data Acquisition (DAQ) Modular Systems
High-speed industrial DAQ modules for vibration analysis, machine-condition monitoring and power-quality analysis benefit from the LTC2155IUP-14's high sample rate per channel and dual-channel density. The exposed-pad QFN package spreads heat effectively when modules are stacked densely in a PXI / PXIe chassis. Two channels per chip minimize FPGA SERDES lanes and BOM cost compared to using two discrete single-channel ADCs. Configure one channel for high-speed vibration capture and the second for slower auxiliary thermocouple / process-signal multiplex through an external front-end MUX - the pipelined latency is constant and deterministic, simplifying trigger alignment.
推荐
推荐产品汇总
工程参考数据： LTC2155IUP-14 ——对比、设计指导和合规信息。
选型指南
与替代料对比
| 参数 | 本产品 | LTC2155CUP-14#PBF | LTC2156IUP-14#PBF | LTC2157IUP-14#PBF | LTC2155IUP-14#TRPBF | LTC2255IUP-14#PBF |
|---|---|---|---|---|---|---|
| Brand | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices |
| Package | 64-QFN (9x9) UP | 64-QFN (9x9) UP - same | 64-QFN (9x9) UP - same | 64-QFN (9x9) UP - same | 64-QFN (9x9) UP - same | 64-QFN (9x9) UP - same |
| Sample Rate (per channel) | 170 Msps | 170 Msps (same) | 210 Msps (+24%) | 250 Msps (+47%) | 170 Msps (same) | 125 Msps (single-channel, -26%) |
| Resolution | 14 bits | 14 bits (same) | 14 bits (same) | 14 bits (same) | 14 bits (same) | 14 bits (same) |
| Number of Channels | 2 (simultaneous) | 2 (simultaneous) | 2 (simultaneous) | 2 (simultaneous) | 2 (simultaneous) | 1 (single-channel) |
| Operating Temperature Range | -40C to +85C (I grade) | 0C to +70C (C grade) | -40C to +85C (I grade) | -40C to +85C (I grade) | -40C to +85C (I grade) | -40C to +85C (I grade) |
| Supply Voltage | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 1.8 V |
关键差异点
- Only dual 14-bit ADC in UP package running at 170 Msps (intermediate speed bin) （对比 LTC2155CUP-14#PBF (170 Msps) vs LTC2156-14 (210 Msps) vs LTC2157-14 (250 Msps))
- I-grade operating range -40C to +85C (vs C-grade 0C to +70C) （对比 LTC2155CUP-14#PBF)
- On-chip dither generator for improved SFDR at small input levels （对比 Comparable dual 14-bit ADCs (e.g. ADS62P49) typically lack on-chip dither)
设计说明
Route the analog inputs (INA+/INA-, INB+/INB-) as 100-ohm differential pairs from the transformer or balun secondary directly into the ADC input pins, keeping the pair length matched within 0.5 mm and as short as possible. Place the differential 100-ohm termination resistor across the input pins immediately adjacent to the package (within 2-3 mm) to suppress reflection and preserve 600 MHz full-power bandwidth per the Analog Devices datasheet 21576514fb. Provide a continuous ground reference plane on layer 2 under the analog traces - never split the ground plane. Estimated: assuming FR4 with Er=4.2, a 50-ohm single-ended microstrip on 0.2 mm dielectric requires approximately 0.40 mm trace width; adjust during stackup review.
Power the 1.8 V analog (AVDD) and 1.8 V digital (DVDD) rails from separate low-noise LDO regulators (or from a common rail through ferrite beads and decoupling networks) to prevent the noisy digital serializer from corrupting the analog front-end. According to the Analog Devices datasheet 21576514fb, use a 10 uF bulk + 0.1 uF + 1 nF + 10 nF decoupling network on each AVDD/DVDD pin, placing the smallest-value cap closest to the pin. Add a decoupling cap close to the OVDD output-driver supply pin as well. Estimated: at 170 Msps the LTC2155IUP-14 draws approximately 250 mW per channel; ensure the LDO can supply at least 280 mA at 1.8 V with headroom for transient spikes.
Common pitfalls when using the LTC2155IUP-14: (1) failing to solder the QFN exposed thermal pad to the PCB ground plane - this pads reduces ground impedance and provides heat dissipation; if left open the device will overheat and parameters will drift; (2) operating single-ended instead of differential - the ADC requires differential inputs to meet the datasheet's specified SFDR of 90 dBFS; (3) forgetting the SDO external 2k pull-up resistor - per the Analog Devices datasheet, if you read back register contents through SDO you must provide an external pull-up because SDO is open-drain with 200 ohm pull-down; (4) launching a calibration sequence on power-up without waiting the required number of clock cycles before valid data appears - check the datasheet's startup timing diagram.
Treat the LVDS output pairs (OUT+, OUT-, DCO+, DCO-, FCO+, FCO-) as 100-ohm differential pairs routed to the FPGA capture bank with a continuous ground reference on an adjacent layer. Keep the LVDS traces short (under 80 mm preferred at 170 Msps DDR) and length-matched within 1 mm within a pair and within 5 mm across all pairs to maintain proper DDR setup/hold margin at the FPGA. Place a 100-ohm differential termination resistor across each LVDS pair at the FPGA bank, not at the ADC end - the LVDS driver impedance is internal to the chip. Reference: the Analog Devices datasheet 21576514fb Figure 3 (LVDS output termination scheme).
合规信息
RoHS-compliant per the #PBF ordering code suffix on the Analog Devices / Linear Technology ordering info. The part does not carry AEC-Q100 qualification - it is not marketed as automotive-grade. Halogen-free and conflict-mineral declarations were not surfaced in the verified web data; set to 'unknown' rather than assumed.
