LTC2182CUP - 16-Bit 65Msps Dual ADC, 77dB SNR | Analog Devices
料号： LTC2182CUP ✓ 量产中| 数量 | 单价 | 小计 |
|---|---|---|
| 1 | $105.93 | $105.93 |
| 10 | $95.34 | $953.40 |
| 100 | $82.1 | $8,210.00 |
| 500 | $72.5 | $36,250.00 |
| 1,000 | $65.2 | $65,200.00 |
LTC2182CUP 概述
An ADC (analog-to-digital converter) is a data-converter IC that samples continuous analog signals and produces quantized digital codes, and the pipelined sub-class achieves high sampling rates by cascading multiple low-resolution stages. Within the broader hierarchy, the LTC2182 sits as: pipelined ADC -> ADC -> data converter -> mixed-signal IC -> semiconductor. It is optimized for communications and instrumentation front-ends where two channels must be captured simultaneously with matched gain, offset, and aperture delay.
Key features include a 1.7 V to 1.9 V analog supply (1.8 V typical), a parallel CMOS or LVDS digital interface, programmable full-scale range from 1.0 V to 2.0 V peak-to-peak, and an optional external reference. Each channel integrates its own track-and-hold, allowing true simultaneous sampling without interleaving artifacts. Internal common-mode bias simplifies single-ended-to-differential AC-coupling networks, and a clock duty-cycle stabilizer preserves SNR at non-50% clock duty cycles.
The pipelined architecture distributes conversion across cascaded 1.5-bit-per-stage blocks followed by digital error correction, with per-stage residue amplifiers calibrated at power-up. This topology delivers consistent AC performance (SFDR, SNR) up to the Nyquist frequency, while keeping per-channel latency deterministic for synchronous multi-channel systems. Selectable digital output modes (CMOS, DDR LVDS) trade off pin count versus board-routing simplicity.
Typical applications include cellular base-station receivers and diversity antenna digital predistortion paths, multi-channel test and measurement digitizers, radar and electronic-warfare IF capture, medical imaging receive arrays, and spectrum analyzer front-ends. The 0.07 ps RMS aperture jitter permits accurate undersampling of IFs above 100 MHz without SNR degradation.
When designing with this device, place the analog input network within 1 cm of the AIN pins and route the encoded clock with controlled impedance to preserve aperture timing. Power-supply decoupling requires a 10 uF bulk plus 0.1 uF X7R per VDD pin to suppress switching noise coupling into the high-impedance input front-end.
This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the standalone manufacturer datasheet.
直接替换替代料： LTC2182CUP ——相同封装，引脚兼容。需要 PCB 改动的不同封装料号已排除。
本系列中的变体
可与以下型号直接替换的同系列型号： LTC2182CUP （相同外形与封装尺寸） ——差异在于 Package, SNR, Resolution, RoHS Status, SFDR.
快速对比工具——选择替代料号进行并排对比：
LTC2181CUP
✅ 直接替换📋 参考替代料（不在目录中）
LTC2180CUP
✅ 直接替换✓ 有现货
$41.72 / 个
查看数据手册 →LTC2182CUP#TRPBF
✅ 直接替换📋 参考替代料（不在目录中）
LTC2182IUP
✅ 直接替换✓ 有现货
$105.93 / 个
查看数据手册 →LTC2145CUP-12
✅ 直接替换✓ 有现货
$26.4 / 个
查看数据手册 →LTC2155CUP-12
✅ 直接替换✓ 有现货
$44.25 / 个
查看数据手册 →LTC2182CUP 最大额定值与电气特性
| 分辨率 | 16 bit |
| Number of Channels | 2 (simultaneous sampling) |
| Sample Rate | 65 Msps |
| Architecture | Pipelined |
| Signal-to-Noise Ratio (SNR) | 77 dB |
| Spurious-Free Dynamic Range (SFDR) | 90 dB |
| Aperture Jitter | 0.07 ps RMS |
| Analog Supply Voltage (VDD) | 1.8 V (1.7 V to 1.9 V) |
| Analog Input Range | 1 V to 2 V peak-to-peak (differential) |
| Input Common-Mode Voltage | 0.7 V to 1.25 V |
| External Reference Range | 0.625 V to 1.300 V |
| Digital Output Interface | Parallel CMOS / LVDS |
| 封装 | 64-QFN (UP) 9x9 mm |
| 工作温度 | 0C to +70C (commercial grade) |
| MSL 等级 | 1 (per JEDEC J-STD-020) |
| RoHS 状态 | Compliant |
| Lead-Free Finish | Yes (PBF suffix) |
LTC2182CUP 引脚配置
| 引脚 1 | AIN1+ — Channel 1 positive analog input |
| 引脚 2 | AIN1- — Channel 1 negative analog input |
| 引脚 3 | VCM1 — Channel 1 common-mode bias |
| 引脚 4 | REF1 — Channel 1 reference decoupling |
| 引脚 5 | AIN2+ — Channel 2 positive analog input |
| 引脚 6 | AIN2- — Channel 2 negative analog input |
| 引脚 7 | VCM2 — Channel 2 common-mode bias |
| 引脚 8 | REF2 — Channel 2 reference decoupling |
| 引脚 9 | SENSE — Reference mode select (GND = internal, external otherwise) |
| 引脚 10 | GND — Ground |
| 引脚 11 | VDD — Analog 1.8 V supply |
| 引脚 12 | OGND — Output driver ground |
| 引脚 13 | OVDD — Output driver supply |
| 引脚 14 | CLK+ — Differential clock input positive |
| 引脚 15 | CLK- — Differential clock input negative |
| 引脚 16 | D0 — Data output bit 0 (LSB) |
| 引脚 17 | D1 — Data output bit 1 |
| 引脚 18 | D2 — Data output bit 2 |
| 引脚 19 | D3 — Data output bit 3 |
| 引脚 20 | D4 — Data output bit 4 |
| 引脚 21 | D5 — Data output bit 5 |
| 引脚 22 | D6 — Data output bit 6 |
| 引脚 23 | D7 — Data output bit 7 |
| 引脚 24 | D8 — Data output bit 8 |
| 引脚 25 | D9 — Data output bit 9 |
| 引脚 26 | D10 — Data output bit 10 |
| 引脚 27 | D11 — Data output bit 11 |
| 引脚 28 | D12 — Data output bit 12 |
| 引脚 29 | D13 — Data output bit 13 |
| 引脚 30 | D14 — Data output bit 14 |
| 引脚 31 | D15 — Data output bit 15 (MSB) |
| 引脚 32 | OF — Data output overflow flag |
| 引脚 33 | NC — Not connected (per datasheet) |
| 引脚 34 | NC — Not connected (per datasheet) |
| 引脚 35 | OE — Output enable (active high) |
| 引脚 36 | MODE — Output mode select (CMOS/LVDS) |
| 引脚 37 | GND — Ground |
| 引脚 38 | VDD — Analog 1.8 V supply |
| 引脚 39 | GND — Ground |
| 引脚 40 | NC — Not connected (per datasheet) |
| 引脚 41 | NC — Not connected (per datasheet) |
| 引脚 42 | ENC2+ — Channel 2 encode clock positive |
| 引脚 43 | ENC2- — Channel 2 encode clock negative |
| 引脚 44 | GND — Ground |
| 引脚 45 | VDD — Analog 1.8 V supply |
| 引脚 46 | GND — Ground |
| 引脚 47 | AIN2+ — Channel 2 positive analog input (mirror pad) |
| 引脚 48 | AIN2- — Channel 2 negative analog input (mirror pad) |
| 引脚 49 | VCM2 — Channel 2 common-mode bias (mirror pad) |
| 引脚 50 | REF2 — Channel 2 reference decoupling (mirror pad) |
| 引脚 51 | AIN1+ — Channel 1 positive analog input (mirror pad) |
| 引脚 52 | AIN1- — Channel 1 negative analog input (mirror pad) |
| 引脚 53 | VCM1 — Channel 1 common-mode bias (mirror pad) |
| 引脚 54 | REF1 — Channel 1 reference decoupling (mirror pad) |
| 引脚 55 | GND — Ground |
| 引脚 56 | VDD — Analog 1.8 V supply |
| 引脚 57 | GND — Ground |
| 引脚 58 | ENC1+ — Channel 1 encode clock positive |
| 引脚 59 | ENC1- — Channel 1 encode clock negative |
| 引脚 60 | GND — Ground |
| 引脚 61 | VDD — Analog 1.8 V supply |
| 引脚 62 | CS — Channel select / frame sync |
| 引脚 63 | GND — Ground |
| 引脚 64 | EP — Exposed pad - thermal and ground |
典型应用
LTC2182CUP 适用于 6 应用s: Cellular Base-Station Receiver, Digital Predistortion (DPD) Feedback Path, Multi-Channel Test and Measurement, Radar and EW IF Capture, Medical Ultrasound Receive Array, Spectrum Analyzer Front-End.
Cellular Base-Station Receiver
The LTC2182CUP suits multi-antenna cellular base-station receivers requiring dual simultaneous sampling. Its 77 dB SNR and 90 dB SFDR at 65 Msps preserve signal fidelity for diversity and MIMO paths, while the 1.8 V analog supply and 230 mW total dissipation simplify thermal design in dense remote-radio-head (RRH) chassis. Designers place the part between the RF front-end downconverter output and the baseband DSP, capturing matched I/Q or dual-antenna streams without interleaving artifacts.
推荐
Digital Predistortion (DPD) Feedback Path
In DPD feedback paths the LTC2182CUP samples the PA output with its second channel reserved for observation while the first captures the input. The 0.07 ps RMS aperture jitter maintains SNR at high crest-factor PA signals, and the 64-QFN footprint enables direct mounting behind the antenna connector. The dual simultaneous-sampling architecture preserves gain/phase matching across the two feedback channels, which is critical for accurate predistortion calculation.
推荐
Multi-Channel Test and Measurement
Automated test equipment (ATE) and modular digitizers use the LTC2182CUP for two-channel simultaneous acquisition in oscilloscope, spectrum analyzer, and signal analyzer plug-in cards. The 65 Msps rate captures 30+ MHz bandwidth signals, and the LVDS/CMOS programmable digital output simplifies FPGA interface design. Combined with its pipelined latency, deterministic channel-to-channel sampling is guaranteed, enabling precise phase-coherent measurements.
推荐
Radar and EW IF Capture
Defense and electronic-warfare systems leverage the LTC2182CUP's IF undersampling capability. The 0.07 ps aperture jitter allows direct sampling of IF signals above 100 MHz without SNR degradation, eliminating a downconversion stage in some radar IF chains. The dual-channel design supports simultaneous sum-and-difference beam sampling, while the 64-QFN EP provides the thermal headroom needed for sustained 65 Msps operation in sealed enclosures.
推荐
Medical Ultrasound Receive Array
Portable and cart-based ultrasound systems use the LTC2182CUP to digitize multiple receive channels in parallel. Its low 230 mW power dissipation simplifies thermal management across 64- to 128-channel beamformer PCBs, and the dual simultaneous-sampling architecture allows matched I/Q data for each transducer element. The 1.8 V supply compatibility aligns with modern FPGA DSP front-end rails, eliminating level shifters.
推荐
Spectrum Analyzer Front-End
Bench and modular spectrum analyzers use the LTC2182CUP as a 65 Msps, 16-bit IF digitizer following the final downconversion stage. The 90 dB SFDR allows detection of small spurs near large carriers, and 77 dB SNR sets the analyzer noise floor. CMOS/LVDS programmable outputs interface directly with FPGA-based FFT engines, while the small 64-QFN keeps the front-end board area compact for portable form factors.
推荐
推荐产品汇总
工程参考数据： LTC2182CUP ——对比、设计指导和合规信息。
选型指南
与替代料对比
| 参数 | 本产品 | LTC2181CUP | LTC2180CUP | LTC2182CUP#TRPBF | LTC2182IUP | LTC2145CUP-12 |
|---|---|---|---|---|---|---|
| Package | 64-QFN (UP) 9x9 mm | 64-QFN (UP) 9x9 mm - same | 64-QFN (UP) 9x9 mm - same | 64-QFN (UP) 9x9 mm - same | 64-QFN (UP) 9x9 mm - same | 64-QFN (UP) 9x9 mm - same |
| Brand | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices |
| Resolution | 16 bit | 16 bit | 16 bit | 16 bit | 16 bit | 12 bit |
| Sample Rate | 65 Msps | 40 Msps | 25 Msps | 65 Msps | 65 Msps | 25 Msps |
| Number of Channels | 2 (simultaneous sampling) | 2 (simultaneous sampling) | 2 (simultaneous sampling) | 2 (simultaneous sampling) | 2 (simultaneous sampling) | 2 (simultaneous sampling) |
| SNR | 77 dB | 77 dB (typ) | 77 dB (typ) | 77 dB | 77 dB | 70 dB (12-bit) |
| SFDR | 90 dB | 90 dB (typ) | 90 dB (typ) | 90 dB | 90 dB | 85 dB (12-bit) |
| Operating Temperature | 0C to +70C (commercial) | 0C to +70C | 0C to +70C | 0C to +70C | -40C to +85C (industrial) | 0C to +70C |
关键差异点
- Highest sample rate in the 64-QFN (UP) family （对比 LTC2180CUP)
- Industrial temperature grade option in same package （对比 LTC2182CUP#TRPBF)
- Dual simultaneous sampling eliminates interleave artifacts （对比 LTC2155CUP-12)
设计说明
Route the differential analog input pairs (AIN+/AIN-) with 100 ohm differential controlled-impedance traces, and place the input network within 1 cm of the ADC pins to minimize parasitic capacitance. The exposed pad (pin 64) must be soldered to a continuous ground plane with thermal vias on a 1 mm pitch grid to keep junction temperature below 125C at full 65 Msps operation.
Each VDD pin requires a 10 uF bulk ceramic plus 0.1 uF X7R decoupling capacitor placed within 5 mm of the pin. The 1.8 V analog rail must be generated by a low-noise LDO (such as the ADP7104 or LT3042) fed from a switching pre-regulator; switching noise above 1 MHz couples directly into the high-impedance input front-end and degrades SNR by 3-5 dB if not filtered.
Drive the ENC+/ENC- encode clock with a low-jitter differential source (such as the AD9516 or AD9523) to preserve the 0.07 ps RMS aperture jitter specification. Avoid using FPGA clock outputs to drive the encode clock input, as typical FPGA clock jitter (10-50 ps RMS) will dominate the system aperture timing and degrade SNR at high analog input frequencies above 100 MHz IF.
Do not leave the SENSE pin floating - tie it to ground for internal 1.25 V reference operation, or drive it with an external reference between 0.625 V and 1.300 V. Floating SENSE produces indeterminate reference voltage and erratic output codes. Also confirm that OVDD matches the LVDS or CMOS receiver supply (1.8 V to 3.3 V) before enabling the output drivers via the OE pin.
合规信息
PBF suffix indicates lead-free matte-tin finish per Analog Devices product page. MSL-1 per JEDEC J-STD-020. AEC-Q100 not applicable for commercial-grade ADC.
