LTC2180CUP - 16-Bit 25Msps Dual ADC, Low Power | Analog Devices
料号： LTC2180CUP ✓ 量产中| 数量 | 单价 | 小计 |
|---|---|---|
| 1 | $69.13 | $69.13 |
| 10 | $62.22 | $622.20 |
| 100 | $55.3 | $5,530.00 |
| 500 | $48.51 | $24,255.00 |
| 1,000 | $41.72 | $41,720.00 |
LTC2180CUP 概述
A pipelined ADC is a converter topology that processes the analog input through cascaded low-resolution stages, producing a high-resolution digital word at high conversion rates with relatively low latency. The dual-channel configuration places two complete ADC cores on a single substrate so each can be sampled on the same clock edge, enabling accurate I/Q or differential acquisition. Compared with sigma-delta ADCs, pipeline converters offer substantially wider input bandwidths (here 400MHz analog input) at the cost of somewhat higher noise spectral density. This makes the LTC2180 a representative entry in the precision pipeline ADC segment used in instrumentation, test equipment, communications transceivers, and medical imaging front-ends.
Key features include selectable 1.5Vpp or 2Vpp input ranges, an internal high-precision reference that eliminates an external reference IC, optional CMOS or LVDS digital outputs for flexible FPGA/ASIC interfacing, and a low-jitter clock multiplier that allows operation with a low-frequency external reference clock. The LVDS path supports DDR mode for tighter board-level timing margins at high sample rates.
Internally, the device uses a 16-stage pipeline architecture with proprietary calibration to maintain linearity over temperature. The exposed thermal pad on the QFN package reduces theta-JA to approximately 21C/W on a 4-layer JEDEC test board, enabling reliable operation at full sample rate without forced-air cooling. Power-down current drops below 1uA per channel, making the device attractive for portable or battery-backed multi-channel instruments.
Typical applications include multi-antenna software-defined radio (SDR) receivers, multi-carrier cellular base-station observation, simultaneous-sampling data acquisition modules, ultrasound beamforming front-ends, and high-end test-and-measurement instruments. Engineers typically deploy the part behind a low-noise differential driver such as the LTC6400 or ADA4937 to fully exploit its dynamic range.
When designing with this device, pay close attention to PCB layout for the analog inputs and clock lines: the exposed pad must be soldered to a continuous ground plane to achieve the specified thermal and electrical performance. Use length-matched LVDS routing to the host FPGA to avoid timing skew between channels and to preserve the 90dB SFDR.
This page synthesizes distributor pricing, drop-in alternatives (LTC2181CUP, LTC2155CUP-12), and practical design notes not found in the manufacturer datasheet alone, including I/Q sample-rate planning and reference-decoupling guidance.
直接替换替代料： LTC2180CUP ——相同封装，引脚兼容。需要 PCB 改动的不同封装料号已排除。
本系列中的变体
可与以下型号直接替换的同系列型号： LTC2180CUP （相同外形与封装尺寸） ——差异在于 Package, Operating Temperature Range, SNR, RoHS Status, Input Range.
快速对比工具——选择替代料号进行并排对比：
LTC2181CUP#PBF
✅ 直接替换📋 参考替代料（不在目录中）
LTC2180IUP#PBF
✅ 直接替换📋 参考替代料（不在目录中）
LTC2155CUP-12
✅ 直接替换 ⚠️ 规格未核验✓ 有现货
$44.25 / 个
查看数据手册 →LTC2156IUP-14
✅ 直接替换 ⚠️ 规格未核验✓ 有现货
$134.1 / 个
查看数据手册 →LTC2145CUP-12
✅ 直接替换 ⚠️ 规格未核验✓ 有现货
$26.4 / 个
查看数据手册 →LTC2180CUP 最大额定值与电气特性
| Part Number | LTC2180CUP |
| 分辨率 | 16 bits |
| Sample Rate (per channel) | 25 Msps |
| Number of Channels | 2 (simultaneous sampling) |
| Architecture | Pipelined |
| Input Type | Differential, 1.5Vpp or 2Vpp selectable |
| Analog Input Bandwidth | 400 MHz |
| SNR | 76.8 dB at 5 MHz input |
| SFDR | 90 dB at 5 MHz input |
| Channel Crosstalk | -110 dB |
| Power Consumption (per channel) | 75 mW (25 Msps) |
| Digital Output | CMOS or LVDS (pin selectable) |
| Integral Nonlinearity (INL) | 1 LSB typ |
| Reference | Internal (external optional) |
| 电源电压 | 1.7V to 1.9V (analog/digital), 3.13V to 3.47V (output driver) |
| 工作温度范围 | 0C to +70C |
| 封装 | QFN-64 (UP) 9x9 mm with exposed pad |
| 安装类型 | Surface Mount |
| RoHS 状态 | Compliant |
LTC2180CUP 引脚配置
| 引脚 1 | OGND — Output driver ground |
| 引脚 2 | OVDD — Output driver supply |
| 引脚 3 | OE — Output enable (logic input) |
| 引脚 4 | SDOUT — Serial data output (SPI configuration) |
| 引脚 5 | SCK — Serial clock input (SPI configuration) |
| 引脚 6 | CS — Chip select for SPI configuration |
| 引脚 7 | SDI — Serial data input (SPI configuration) |
| 引脚 8 | MODE — Digital output mode select (CMOS/LVDS) |
| 引脚 9 | GND — Ground |
| 引脚 10 | VA+ — Analog supply |
| 引脚 11 | GA1+ — Channel 1 analog input positive |
| 引脚 12 | GA1- — Channel 1 analog input negative |
| 引脚 13 | VA+ — Analog supply |
| 引脚 14 | GA2+ — Channel 2 analog input positive |
| 引脚 15 | GA2- — Channel 2 analog input negative |
| 引脚 16 | GND — Ground |
| 引脚 17 | REFH — Reference decoupling high |
| 引脚 18 | REFL — Reference decoupling low |
| 引脚 19 | VREF — Internal reference voltage |
| 引脚 20 | GND — Ground |
| 引脚 21 | SENSE — Reference configuration pin |
| 引脚 22 | VA+ — Analog supply |
| 引脚 23 | GND — Ground |
| 引脚 24 | VA+ — Analog supply |
| 引脚 25 | VA+ — Analog supply |
| 引脚 26 | GND — Ground |
| 引脚 27 | ENC+ — Encode clock input positive |
| 引脚 28 | ENC- — Encode clock input negative |
| 引脚 29 | GND — Ground |
| 引脚 30 | OVDD — Output driver supply |
| 引脚 31 | D0-/D0 — Channel 1 digital output bit 0 (LVDS/CMOS) |
| 引脚 32 | D1-/D1 — Channel 1 digital output bit 1 (LVDS/CMOS) |
| 引脚 33 | D2-/D2 — Channel 1 digital output bit 2 (LVDS/CMOS) |
| 引脚 34 | D3-/D3 — Channel 1 digital output bit 3 (LVDS/CMOS) |
| 引脚 35 | OGND — Output driver ground |
| 引脚 36 | OVDD — Output driver supply |
| 引脚 37 | D4-/D4 — Channel 1 digital output bit 4 (LVDS/CMOS) |
| 引脚 38 | D5-/D5 — Channel 1 digital output bit 5 (LVDS/CMOS) |
| 引脚 39 | D6-/D6 — Channel 1 digital output bit 6 (LVDS/CMOS) |
| 引脚 40 | D7-/D7 — Channel 1 digital output bit 7 (LVDS/CMOS) |
| 引脚 41 | D8-/D8 — Channel 1 digital output bit 8 (LVDS/CMOS) |
| 引脚 42 | D9-/D9 — Channel 1 digital output bit 9 (LVDS/CMOS) |
| 引脚 43 | DA-/DA — Channel 1 data clock (LVDS/CMOS) |
| 引脚 44 | OGND — Output driver ground |
| 引脚 45 | OVDD — Output driver supply |
| 引脚 46 | D0B-/D0B — Channel 2 digital output bit 0 (LVDS/CMOS) |
| 引脚 47 | D1B-/D1B — Channel 2 digital output bit 1 (LVDS/CMOS) |
| 引脚 48 | D2B-/D2B — Channel 2 digital output bit 2 (LVDS/CMOS) |
| 引脚 49 | D3B-/D3B — Channel 2 digital output bit 3 (LVDS/CMOS) |
| 引脚 50 | D4B-/D4B — Channel 2 digital output bit 4 (LVDS/CMOS) |
| 引脚 51 | D5B-/D5B — Channel 2 digital output bit 5 (LVDS/CMOS) |
| 引脚 52 | D6B-/D6B — Channel 2 digital output bit 6 (LVDS/CMOS) |
| 引脚 53 | D7B-/D7B — Channel 2 digital output bit 7 (LVDS/CMOS) |
| 引脚 54 | D8B-/D8B — Channel 2 digital output bit 8 (LVDS/CMOS) |
| 引脚 55 | D9B-/D9B — Channel 2 digital output bit 9 (LVDS/CMOS) |
| 引脚 56 | DB-/DB — Channel 2 data clock (LVDS/CMOS) |
| 引脚 57 | OGND — Output driver ground |
| 引脚 58 | OVDD — Output driver supply |
| 引脚 59 | FRAME-/FRAME — Frame clock output (LVDS/CMOS) |
| 引脚 60 | GND — Ground |
| 引脚 61 | VA+ — Analog supply |
| 引脚 62 | GND — Ground |
| 引脚 63 | VA+ — Analog supply |
| 引脚 64 | GND — Ground (Exposed Pad) |
典型应用
LTC2180CUP 适用于 7 应用s: Multi-Antenna Software-Defined Radio (SDR) Receivers, Multi-Carrier Cellular Base-Station Observation, Simultaneous-Sampling Data Acquisition Modules, Ultrasound Beamforming Front-Ends, High-End Test-and-Measurement Instruments, Industrial Vibration & Acoustic Monitoring, Radar & Lidar Signal Processing Front-Ends.
Multi-Antenna Software-Defined Radio (SDR) Receivers
The LTC2180CUP is well-suited to multi-antenna SDR receivers where two simultaneous 16-bit streams must be captured at IF or baseband. With 25 Msps per channel, 76.8 dB SNR, and -110 dB crosstalk, the part cleanly digitizes wide-bandwidth signals while preserving channel-to-channel phase coherence. Designers typically place the LTC2180CUP behind a low-noise differential driver such as the ADA4937 and route its LVDS outputs to a host FPGA running digital down-conversion. Compared with discrete dual-ADC boards, the integrated clock multiplier simplifies the local-oscillator chain and reduces PCB area in 4G/5G base-station observation receivers.
推荐
Multi-Carrier Cellular Base-Station Observation
In base-station observation receivers, the LTC2180CUP samples two carrier streams simultaneously to enable joint monitoring of uplink spectrum and interference analysis. The 76.8 dB SNR floor provides adequate dynamic range for capturing weak signals in the presence of strong in-band carriers, while the 25 Msps per-channel rate supports carriers up to 10 MHz wide. The selectable 1.5Vpp or 2Vpp full-scale inputs allow direct connection to typical IF transformers, eliminating external attenuator networks. Pin-compatible operation with the LTC2181CUP (40 Msps) and LTC2182CUP (65 Msps) lets the same PCB platform scale across multiple base-station classes.
推荐
Simultaneous-Sampling Data Acquisition Modules
Portable and rack-mounted data acquisition systems benefit from the LTC2180CUP's two simultaneously sampled channels and integrated internal reference, which reduces component count on the analog front end. The 25 Msps sample rate per channel is well matched to capturing transient events on instrumentation-quality input signals, while the 90 dB SFDR ensures spurious-free performance on vibration and acoustic test platforms. The exposed-pad QFN-64 package allows operation without a heatsink in most environments, keeping module heights compact for PXI or LXI installations.
推荐
Ultrasound Beamforming Front-Ends
Ultrasound beamforming systems rely on multiple channels sampled at exactly the same instant, which the LTC2180CUP provides by integrating two ADC cores with a shared clock. The 76.8 dB SNR supports tissue-depth penetration requirements of typical 4-8 MHz probes when paired with a low-noise preamp, while the 400 MHz analog input bandwidth accommodates higher harmonics needed for harmonic imaging. The -110 dB channel crosstalk is critical for suppressing beamforming artifacts. Designers frequently pair the LTC2180CUP with an FPGA that performs delay-and-sum beamforming across many cascaded parts.
推荐
High-End Test-and-Measurement Instruments
Instruments such as oscilloscopes, spectrum analyzers, and digitizers benefit from the LTC2180CUP's -90 dB SFDR when digitizing complex mixed-signal waveforms. The dual-channel arrangement allows trigger and signal paths to be digitized in parallel, eliminating timing skew that would otherwise degrade time-interleaved measurements. With pin-compatible higher-speed variants (LTC2181CUP, LTC2182CUP), the same platform can scale across 25-65 Msps instrument families. The internal precision reference provides 16-bit INL stability required for bench-instrument accuracy.
推荐
Industrial Vibration & Acoustic Monitoring
Predictive maintenance and structural-health monitoring systems use the LTC2180CUP to capture vibration and acoustic waveforms simultaneously from multiple sensor locations. Its 76.8 dB SNR extends usable dynamic range to micro-g accelerometer signals, while the 25 Msps rate prevents aliasing of high-frequency mechanical resonances. The exposed-pad QFN-64 package and industrial-temperature LTC2180IUP variant both support continuous operation in harsh factory environments. The CMOS/LVDS selectable output simplifies interfacing to industrial FPGAs without external level shifters.
推荐
Radar & Lidar Signal Processing Front-Ends
Phased-array radar and lidar receivers digitize I/Q baseband signals where the LTC2180CUP's simultaneous sampling preserves the relative phase between two channels. The 90 dB SFDR ensures spurious-free dynamic range required for distinguishing small targets from environmental clutter, while 400 MHz analog input bandwidth handles wide instantaneous IF bandwidths for chirped or spread-spectrum waveforms. Designers typically cascade multiple LTC2180CUPs in a tiled fashion to support larger antenna arrays, each timed via the integrated clock multiplier and LVDS interface.
推荐
推荐产品汇总
工程参考数据： LTC2180CUP ——对比、设计指导和合规信息。
选型指南
与替代料对比
| 参数 | 本产品 | LTC2181CUP#PBF | LTC2180IUP#PBF | LTC2155CUP-12 | LTC2156IUP-14 | LTC2145CUP-12 |
|---|---|---|---|---|---|---|
| Brand | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices |
| Package | QFN-64 (UP) 9x9 mm | QFN-64 (UP) 9x9 mm - same | QFN-64 (UP) 9x9 mm - same | QFN-64 (UP) 9x9 mm - same | QFN-64 (UP) 9x9 mm - same | QFN-64 (UP) 9x9 mm - same |
| Resolution | 16 bit | 16 bit | 16 bit | 12 bit | 14 bit | 12 bit |
| Sample Rate per Channel | 25 Msps | 40 Msps | 25 Msps | 25 Msps | 25 Msps | 25 Msps (lower power) |
| Number of Channels | 2 | 2 | 2 | 2 | 2 | 2 |
| Operating Temperature Range | 0C to +70C (C-grade) | 0C to +70C | -40C to +85C (I-grade) | 0C to +70C | -40C to +85C (I-grade) | 0C to +70C |
| Power per Channel | 75 mW | 105 mW | 75 mW | Lower (12-bit) | Lower (14-bit) | Lower |
| Digital Outputs | CMOS / LVDS | CMOS / LVDS | CMOS / LVDS | CMOS / LVDS | CMOS / LVDS | CMOS / LVDS |
| Internal Reference | Yes | Yes | Yes | Yes | Yes | Yes |
| RoHS / Lead-Free | RoHS Compliant | RoHS Compliant | RoHS Compliant | RoHS Compliant | RoHS Compliant | RoHS Compliant |
关键差异点
- Best price/performance ratio for 16-bit 25 Msps dual conversion （对比 LTC2181CUP#PBF)
- Industrial temperature option in same footprint （对比 LTC2180IUP#PBF)
- Pin-compatible with higher-speed 40 Msps and 65 Msps variants （对比 LTC2182CUP#PBF)
设计说明
The 64-pin QFN (UP) exposed thermal pad must be soldered to a continuous low-impedance ground plane with at least 9 thermal vias (0.3 mm drill on 0.5 mm pitch) per the Analog Devices layout guide. Skip-via patterns should not be used because they create inductance hotspots that shift the operating temperature and degrade SFDR. Maintain a 4-layer stack-up with dedicated VA+ and GND planes adjacent to the top analog layer.
Route the ENC+ and ENC- differential encode clock lines with 100 ohm differential impedance and matched length to within 50 mil of the analog input traces. Keep analog inputs (GA1+/GA1-, GA2+/GA2-) length-matched to within 25 mil to preserve simultaneous-sampling timing. Decouple each VA+ pin with a 10 uF ceramic plus a 0.1 uF X7R placed within 50 mil of the pin.
Use the LVDS digital output mode (set via MODE pin) at sample rates above 10 Msps to maintain timing margin at the FPGA receiver; CMOS outputs are recommended only for short-trace capture boards. Maintain 100 ohm differential termination at the receiving FPGA bank and avoid using CMOS termination resistors. For GPIO-style fanout to multiple FPGAs, prefer LVDS buffers like the FIN1047 or DS90LV001.
Do not supply the OVDD rail before the VA+ rail, which can cause latch-up through ESD diodes; always ramp VA+ first and apply ENC clock only after both rails are stable. Designers must also avoid leaving SENSE floating - tying it to VA+ selects the internal reference, while tying it to ground selects an external reference mode, and leaving it floating causes unpredictable behavior at power-on.
Estimated: At 25 Msps full-rate operation, total power dissipation is about 150 mW (75 mW per channel) plus 30 mW OVDD; on a 4-layer JEDEC board this maps to roughly +5C junction rise. Drop OVDD current by enabling the OE pin low in power-down mode to achieve <1 uA total quiescent current suitable for battery-backed systems.
合规信息
RoHS compliant per Analog Devices product page. Lead-free finish per datasheet 218210f ordering information. AEC-Q100 not applicable (industrial/commercial ADC, not automotive qualified). Halogen-free status not explicitly stated - default to unknown.
