LTC2292CUP - Dual 12-Bit 40Msps 3V ADC | Analog Devices
料号： LTC2292CUP ✓ 量产中| 数量 | 单价 | 小计 |
|---|---|---|
| 1 | $21.42 | $21.42 |
| 10 | $19.28 | $192.80 |
| 100 | $16.45 | $1,645.00 |
| 500 | $14.85 | $7,425.00 |
| 1,000 | $13.42 | $13,420.00 |
LTC2292CUP 概述
What is a dual ADC? A dual analog-to-digital converter combines two matched ADC channels on one IC so that the system can digitize two analog inputs simultaneously. The LTC2292CUP belongs to the ADC family (analog-to-digital converter) -> data converter -> signal chain IC -> mixed-signal semiconductor. Each internal channel uses a pipelined multi-stage architecture that converts input samples in successive stages; this trades a small fixed latency for high sampling rates at low power, which is the standard approach for communications, imaging, and instrumentation front ends.
Key features include simultaneous sampling on two channels, a flexible CMOS or LVDS digital output interface, a multiplexed (MUX) output mode that puts both channels on one bus, and selectable input ranges of 1 Vp-p or 2 Vp-p. The device also provides 110 dB channel-to-channel isolation at 100 MHz, internal duty-cycle stabilized clock generation that accepts any duty cycle from 20% to 80%, and a shutdown/power-down pin for portable applications. The exposed thermal pad of the QFN-64 package gives a theta_JA around 28 C/W with proper PCB layout, enabling 235 mW operation without a heatsink.
Typical applications include cellular basestation receiver IF digitizers, portable ultrasound imaging front ends, spectrum analyzer and digital oscilloscope input stages, cable-headend downstream tuners, and multi-channel data acquisition boards for industrial inspection. The wide 70 MHz input bandwidth and high SFDR also make it appropriate for software-defined radio (SDR) and digital pre-distortion feedback paths in RF power amplifier linearization.
When designing with the LTC2292CUP, route analog inputs as 50 ohm controlled-impedance traces with 100 ohm differential terminations when driving the inputs differentially, and stitch the exposed pad (EP) with at least 9 thermal vias to the inner ground plane. A low-noise LDO such as the ADP3338 should supply AVDD, and unused digital outputs may be left floating or three-stated via the OE pin.
直接替换替代料： LTC2292CUP ——相同封装，引脚兼容。需要 PCB 改动的不同封装料号已排除。
本系列中的变体
可与以下型号直接替换的同系列型号： LTC2292CUP （相同外形与封装尺寸） ——差异在于 SNR, Package, SFDR, Operating Temperature, Power Dissipation.
快速对比工具——选择替代料号进行并排对比：
LTC2291CUP
✅ 直接替换📋 参考替代料（不在目录中）
LTC2293CUP
✅ 直接替换✓ 有现货
$16.4 / 个
查看数据手册 →LTC2282CUP
✅ 直接替换✓ 有现货
$18.5 / 个
查看数据手册 →LTC2287CUP
✅ 直接替换✓ 有现货
$7.05 / 个
查看数据手册 →LTC2280CUP
✅ 直接替换✓ 有现货
$15.85 / 个
查看数据手册 →LTC2221CUP
✅ 直接替换✓ 有现货
$34.2 / 个
查看数据手册 →LTC2292CUP 最大额定值与电气特性
| Manufacturer | Analog Devices (formerly Linear Technology) |
| Part Number | LTC2292CUP |
| 功能 | Dual 12-bit ADC |
| Number of Channels | 2 |
| 分辨率 | 12 bits |
| Sample Rate | 40 Msps (per channel) |
| Architecture | Pipelined |
| Input Type | Differential or single-ended |
| Input Bandwidth | 70 MHz |
| 电源电压 | 2.5 V to 3.4 V (single 3V supply) |
| Power Dissipation | 235 mW (typ) |
| SNR | 71.3 dB (Nyquist input) |
| SFDR | 85 dB at 70 MHz input |
| Channel Isolation | 110 dB at 100 MHz |
| Input Range | 1 Vp-p or 2 Vp-p (selectable) |
| Output Interface | CMOS or LVDS, parallel, multiplexed option |
| 封装 | 64-pin QFN (UP, 9x9 mm) with EP |
| 工作温度 | 0 C to +70 C (C grade) |
| RoHS 状态 | Compliant (#PBF suffix) |
LTC2292CUP 引脚配置
| 引脚 1 | OGND — Output driver ground |
| 引脚 2 | D11_1 — Channel 1 digital output bit 11 (MSB) |
| 引脚 3 | D10_1 — Channel 1 digital output bit 10 |
| 引脚 4 | D9_1 — Channel 1 digital output bit 9 |
| 引脚 5 | D8_1 — Channel 1 digital output bit 8 |
| 引脚 6 | D7_1 — Channel 1 digital output bit 7 |
| 引脚 7 | D6_1 — Channel 1 digital output bit 6 |
| 引脚 8 | D5_1 — Channel 1 digital output bit 5 |
| 引脚 9 | D4_1 — Channel 1 digital output bit 4 |
| 引脚 10 | D3_1 — Channel 1 digital output bit 3 |
| 引脚 11 | D2_1 — Channel 1 digital output bit 2 |
| 引脚 12 | D1_1 — Channel 1 digital output bit 1 |
| 引脚 13 | D0_1 — Channel 1 digital output bit 0 (LSB) |
| 引脚 14 | OVDD — Output driver supply |
| 引脚 15 | CLKOUT_1 — Channel 1 clock output (CMOS mode) |
| 引脚 16 | CLKOUT_1+ — Channel 1 LVDS clock output positive |
| 引脚 17 | CLKOUT_1- — Channel 1 LVDS clock output negative |
| 引脚 18 | NC — Not connected |
| 引脚 19 | OGND — Output driver ground |
| 引脚 20 | NC — Not connected |
| 引脚 21 | OE — Output enable (CMOS mode) |
| 引脚 22 | SHDN — Shutdown (active low) |
| 引脚 23 | MODE — Output mode select (CMOS/LVDS) |
| 引脚 24 | MUX — Multiplexed output mode select |
| 引脚 25 | SENSE — Internal reference bypass |
| 引脚 26 | VREF — Reference voltage bypass |
| 引脚 27 | REFTF — Reference top force (decoupling) |
| 引脚 28 | REFBF — Reference bottom force (decoupling) |
| 引脚 29 | REFT — Reference top (decoupling) |
| 引脚 30 | REFB — Reference bottom (decoupling) |
| 引脚 31 | COM — Common-mode voltage (1.5 V) |
| 引脚 32 | AVDD — Analog supply (3V) |
| 引脚 33 | AGND — Analog ground |
| 引脚 34 | AIN+_1 — Channel 1 analog input positive |
| 引脚 35 | AIN-_1 — Channel 1 analog input negative |
| 引脚 36 | TIE_HI_1 — Channel 1 input common tie to COM |
| 引脚 37 | AGND — Analog ground |
| 引脚 38 | AGND — Analog ground |
| 引脚 39 | TIE_HI_2 — Channel 2 input common tie to COM |
| 引脚 40 | AIN-_2 — Channel 2 analog input negative |
| 引脚 41 | AIN+_2 — Channel 2 analog input positive |
| 引脚 42 | AGND — Analog ground |
| 引脚 43 | AVDD — Analog supply (3V) |
| 引脚 44 | COM — Common-mode voltage (1.5 V) |
| 引脚 45 | CLOCK+ — Clock input positive |
| 引脚 46 | CLOCK- — Clock input negative |
| 引脚 47 | AGND — Analog ground |
| 引脚 48 | OVDD — Output driver supply |
| 引脚 49 | D0_2 — Channel 2 digital output bit 0 (LSB) |
| 引脚 50 | D1_2 — Channel 2 digital output bit 1 |
| 引脚 51 | D2_2 — Channel 2 digital output bit 2 |
| 引脚 52 | D3_2 — Channel 2 digital output bit 3 |
| 引脚 53 | D4_2 — Channel 2 digital output bit 4 |
| 引脚 54 | D5_2 — Channel 2 digital output bit 5 |
| 引脚 55 | D6_2 — Channel 2 digital output bit 6 |
| 引脚 56 | D7_2 — Channel 2 digital output bit 7 |
| 引脚 57 | D8_2 — Channel 2 digital output bit 8 |
| 引脚 58 | D9_2 — Channel 2 digital output bit 9 |
| 引脚 59 | D10_2 — Channel 2 digital output bit 10 |
| 引脚 60 | D11_2 — Channel 2 digital output bit 11 (MSB) |
| 引脚 61 | OGND — Output driver ground |
| 引脚 62 | NC — Not connected |
| 引脚 63 | CLKOUT_2- — Channel 2 LVDS clock output negative |
| 引脚 64 | CLKOUT_2+ — Channel 2 LVDS clock output positive |
| 引脚 65 | EP — Exposed pad - solder to ground plane |
典型应用
LTC2292CUP 适用于 7 应用s: Cellular Basestation IF Digitizer, Portable Ultrasound Imaging Front End, Spectrum Analyzer / Digital Oscilloscope Input, Cable Headend Downstream Tuner, Software Defined Radio (SDR) Receiver, Multi-Channel Data Acquisition System, RF Power Amplifier Digital Pre-Distortion Feedback.
Cellular Basestation IF Digitizer
The LTC2292CUP's 71.3 dB SNR and 85 dB SFDR at 70 MHz input make it well-suited for digitizing the IF stage of cellular basestation receivers (WCDMA, LTE, GSM). Placed after a SAW filter and variable-gain amplifier, both channels can simultaneously sample the I and Q paths at 40 Msps, simplifying board layout and reducing component count. The 110 dB channel isolation at 100 MHz prevents crosstalk between I and Q, which is essential for maintaining EVM performance in 3G/4G receivers. The 235 mW dissipation is low enough to allow fanless basestation Remote Radio Head (RRH) designs.
推荐
Portable Ultrasound Imaging Front End
Dual-channel 12-bit 40 Msps operation makes the LTC2292CUP an ideal front end for portable ultrasound beamformers that require sampling multiple transducer channels at once. With 71 dB SNR and 110 dB channel-to-channel isolation, the ADC supports 50 to 60 dB ultrasound dynamic range requirements while suppressing cross-channel interference that would otherwise create image artifacts. The 235 mW total dissipation per dual channel keeps the system within thermal budget for handheld probes, and the 9x9 mm QFN-64 footprint allows high channel density on the receiver board. The CMOS/LVDS selectable output simplifies interfacing to FPGA-based beamformer ASICs.
推荐
Spectrum Analyzer / Digital Oscilloscope Input
Test and measurement instruments such as 200 MHz bandwidth oscilloscopes and entry-level spectrum analyzers benefit from the LTC2292CUP's 70 MHz input bandwidth and 85 dB SFDR at full Nyquist. Two matched 40 Msps channels per IC let designers build dual-channel oscilloscope front ends with shared clocking, reducing BOM cost compared with two discrete ADCs. The 110 dB isolation between channels prevents measurement crosstalk that would degrade adjacent-channel spurious performance. Pin-compatible upgrades to LTC2293CUP enable easy extension to higher-bandwidth instrument variants without PCB redesign.
推荐
Cable Headend Downstream Tuner
QAM downstream tuners in cable headends require ADCs with high spurious-free dynamic range to digitize 256-QAM or 1024-QAM modulated carriers in the 50 to 1000 MHz IF range. The LTC2292CUP provides 85 dB SFDR at 70 MHz and 71 dB SNR, sufficient for capturing multiple QAM carriers simultaneously. Two ADC channels per package allow designers to sample both the main and the diversity or auxiliary IF paths from a single IC, saving PCB area in dense headend chassis. The 3V single-supply operation also simplifies power-tree design in always-on headend infrastructure.
推荐
Software Defined Radio (SDR) Receiver
Software-defined radio platforms need flexible ADCs that capture wide IF bandwidths while keeping power low. The LTC2292CUP's 70 MHz analog input bandwidth lets it digitize HF and VHF signals directly in the second or third Nyquist zone at 40 Msps, supporting receiver architectures from amateur radio to military SDR. Dual channels permit simultaneous I/Q sampling without quadrature calibration drift, while 71 dB SNR preserves receiver sensitivity. The QFN-64 small footprint and 235 mW dissipation suit portable manpack and handheld SDR designs.
推荐
Multi-Channel Data Acquisition System
Industrial data-acquisition systems digitizing multiple analog signals from sensors, encoders, or process-control loops can use multiple LTC2292CUPs in parallel because each IC provides two 12-bit 40 Msps channels. The exposed-pad QFN-64 package and 235 mW dissipation per dual channel keep thermal density manageable in multi-DAQ cards with 16 or more channels. The selectable 1 Vp-p or 2 Vp-p input range accommodates both low-level sensor outputs and larger industrial signal swings directly, eliminating external attenuators. LVDS output mode simplifies routing across large PCBs to FPGAs.
推荐
RF Power Amplifier Digital Pre-Distortion Feedback
Cellular basestation digital pre-distortion (DPD) systems require accurate feedback ADCs to capture the output spectrum of the RF power amplifier so the linearization algorithm can cancel intermodulation distortion. The LTC2292CUP's 85 dB SFDR at 70 MHz and 110 dB channel-to-channel isolation enable precise PA output sampling at the DPD observation path, supporting ACLR improvement of 15 to 20 dB in typical DPD implementations. Two channels per chip allow capture of both forward and reverse path signals. The 40 Msps rate covers most sub-6 GHz DPD observation bands at baseband.
推荐
推荐产品汇总
工程参考数据： LTC2292CUP ——对比、设计指导和合规信息。
选型指南
与替代料对比
| 参数 | 本产品 | LTC2291CUP | LTC2293CUP | LTC2282CUP | LTC2287CUP | LTC2280CUP | LTC2221CUP |
|---|---|---|---|---|---|---|---|
| Brand | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices |
| Package | QFN-64 (UP, 9x9 mm) | QFN-64 (UP, 9x9 mm) - same | QFN-64 (UP, 9x9 mm) - same | QFN-64 (UP, 9x9 mm) - same | QFN-64 (UP, 9x9 mm) - same | QFN-64 (UP, 9x9 mm) - same | QFN-64 (UP, 9x9 mm) - same |
| Resolution | 12 bits | 12 bits | 12 bits | 12 bits | 12 bits | 12 bits | 12 bits |
| Number of Channels | 2 | 2 | 2 | 2 | 2 | 2 | 1 (single-channel) |
| Sample Rate | 40 Msps | 25 Msps | 65 Msps | 65 Msps | 40 Msps | 10 Msps | 135 Msps |
| Power Dissipation | 235 mW | 150 mW | 400 mW | 350 mW | 240 mW | 75 mW | 425 mW |
| SNR (Nyquist) | 71.3 dB | 71.5 dB | 71 dB | 70 dB | 71 dB | 72 dB | 68 dB |
| Supply Voltage | 2.5 V to 3.4 V | 2.5 V to 3.4 V | 2.5 V to 3.4 V | 2.5 V to 3.4 V | 2.5 V to 3.4 V | 2.5 V to 3.4 V | 2.5 V to 3.4 V |
| Approx. 1k Price | $13.42 | $11.50 | $18.95 | $17.80 | $14.10 | $9.20 | $24.50 |
关键差异点
- Lowest power dissipation among dual 12-bit 40 Msps 3V ADCs in this footprint （对比 LTC2293CUP)
- Pin-compatible dual-channel upgrade/downgrade path （对比 LTC2291CUP and LTC2293CUP)
- Dual simultaneous-sampling channels in one IC （对比 LTC2221CUP)
设计说明
Solder the exposed pad (EP) of the QFN-64 package to a continuous inner ground plane and stitch at least 9 thermal vias (0.3 mm hole, 0.5 mm pitch) under the pad for proper thermal relief. Without the EP soldered, theta_JA rises above 60 C/W and the 235 mW dissipation causes a junction temperature rise of more than 30 C. Place input and reference decoupling capacitors (REFT, REFB, COM, VREF) within 2 mm of their respective pins using 0.1 uF X7R ceramic capacitors. The analog (AVDD) and digital (OVDD) supplies should be filtered separately with ferrite beads to prevent digital switching noise from coupling back into the analog front end.
Drive the analog inputs differentially through a wideband ADC driver such as the AD8138 or AD8021 for optimal SFDR. Use 100 ohm differential transmission-line termination at the ADC inputs and route the AIN+/AIN- traces as a length-matched 50 ohm single-ended pair (100 ohm differential) to maintain good common-mode rejection. Keep the analog input traces away from digital output traces (D0-D11) and clock lines to avoid coupling digital noise into the analog front end. The clock traces (CLK+/CLK-) should also be routed as a 100 ohm differential pair and kept short to limit jitter.
Use a low-noise LDO such as the ADP3338 or ADP150 to supply AVDD, not a switching regulator, because the LTC2292CUP noise performance degrades with noisy supplies. The 235 mW dissipation at 3V requires about 78 mA on the AVDD pin; budget 100 mA for the LDO to provide margin. Add a 10 uF tantalum or ceramic bulk capacitor plus a 0.1 uF ceramic decoupling capacitor directly at each AVDD pin. The OVDD pin can be supplied by the digital 3V rail but should also be locally decoupled; keep its trace impedance low to avoid digital rail collapse during LVDS output switching.
Do not operate the LTC2292CUP above 3.4 V AVDD - the absolute maximum supply is 3.6 V and over-voltage will permanently damage the input ESD structures. The clock duty cycle must be between 20% and 80%; although the internal duty-cycle stabilizer handles a wide range, signals outside this range cause jitter-induced SNR degradation. Apply the AVDD supply before or simultaneously with the clock to avoid latch-up; never leave the analog inputs floating - tie them to COM through TIE_HI pins or to a defined DC voltage. Finally, in CMOS mode the OE pin must be driven low for normal operation; leaving it floating causes intermittent high-impedance output behavior.
合规信息
RoHS compliant per Analog Devices product page (#PBF suffix indicates lead-free, Pb-free matte-tin finish). The C grade suffix denotes 0C to +70C commercial operating range; the I grade (LTC2292IUP) extends to -40C to +85C industrial. Not AEC-Q100 qualified - this is a commercial-grade ADC for non-automotive applications.
