LTC2299IUP - Dual 14-Bit 80Msps 3V ADC | Analog Devices
料号： LTC2299IUP ✓ 量产中| 数量 | 单价 | 小计 |
|---|---|---|
| 1 | $50.9 | $50.90 |
| 10 | $48.5 | $485.00 |
| 100 | $44.8 | $4,480.00 |
| 500 | $41.2 | $20,600.00 |
| 1,000 | $38.75 | $38,750.00 |
| 3,000 | $35.95 | $107,850.00 |
LTC2299IUP 概述
An ADC (analog-to-digital converter) is a mixed-signal integrated circuit that samples a continuous-time analog waveform and converts each sample into a discrete digital code. Higher-order converters such as pipelined 14-bit parts sit at the high end of the performance spectrum, combining wide input bandwidth with high spurious-free dynamic range, and serve as the critical bridge between analog front ends (amplifiers, filters, mixers) and downstream DSP or FPGA-based processing. The LTC2299IUP belongs to the pipelined ADC sub-family, suitable for multi-carrier base stations, medical imaging receivers, and broadband data acquisition.
Key features include 73 dB SNR and 90 dB SFDR at the 70 MHz input frequency with -1 dBFS amplitude, an input bandwidth greater than 575 MHz, optional internal dither for SFDR improvement, and a low 125 mW power dissipation. The package integrates a thermally efficient exposed pad (eP), and Pin 1 is identified by a top-side dot. The device supports industry-standard CMOS output modes and operates across an industrial temperature grade.
The architecture uses two matched pipelined cores with shared reference and bias circuits. Each pipeline resolves 14 bits in successive 1.5-bit stages, with on-chip output error correction. An internal dither DAC can be enabled via a serial interface to randomize residual stage non-linearities and improve SFDR for repetitive input signals by up to 3 dB in narrowband undersampling applications.
Typical applications include cellular basestation receivers, medical imaging (CT, ultrasound front-ends), cable head-end digitizers, spectrum analysis, and multi-channel data acquisition systems. The dual-channel integration reduces both board area and BOM cost in systems that sample I/Q baseband or two phased-array antennas.
When designing with the LTC2299IUP, treat the exposed pad as the primary thermal path and the primary ground return. Use a low-inductance ground via array directly beneath the eP, separate analog and digital ground planes, and place the input coupling network as close to the analog input pins as possible to preserve the 575 MHz analog input bandwidth.
This page consolidates distributor pricing, industrial-grade temperature range specifications, and drop-in alternatives into a single reference sourced from the manufacturer datasheet and current distributor listings.
直接替换替代料： LTC2299IUP ——相同封装，引脚兼容。需要 PCB 改动的不同封装料号已排除。
本系列中的变体
可与以下型号直接替换的同系列型号： LTC2299IUP （相同外形与封装尺寸） ——差异在于 Package, SNR, Resolution, RoHS Status, SFDR.
快速对比工具——选择替代料号进行并排对比：
LTC2299CUP
✅ 直接替换✓ 有现货
$33.2 / 个
查看数据手册 →LTC2299IUP#PBF
✅ 直接替换📋 参考替代料（不在目录中）
LTC2299IUP#TRPBF
✅ 直接替换📋 参考替代料（不在目录中）
LTC2297IUP
✅ 直接替换✓ 有现货
$27.75 / 个
查看数据手册 →LTC2292CUP
✅ 直接替换✓ 有现货
$13.42 / 个
查看数据手册 →LTC2299IUP 最大额定值与电气特性
| 分辨率 | 14 bits |
| Number of Channels | 2 (dual) |
| 采样率 | 80 Msps |
| Architecture | Pipelined |
| Analog Supply Voltage | 3 V (single) |
| Digital I/O Supply (OVDD) | 1.5 V to 3 V (independent) |
| Power Dissipation | 125 mW typical (per datasheet) |
| SNR | 73 dB at 70 MHz input, -1 dBFS |
| SFDR | 90 dB at 70 MHz input, -1 dBFS |
| Analog Input Bandwidth | 575 MHz |
| Differential Input Range | 1 Vp-p to 2 Vp-p (selectable via SENSE pin per family) |
| Output Format | CMOS, dual data rate |
| Optional Internal Dither | Yes, serial-interface controlled |
| 封装 | 64-QFN (9 mm x 9 mm) with exposed pad |
| Operating Temperature Grade | Industrial (-40C to +85C) |
| 安装类型 | Surface Mount |
| RoHS 状态 | Compliant (PBF suffix) |
LTC2299IUP 引脚配置
| 引脚 1 | OGND — Digital output driver ground |
| 引脚 2 | OVDD — Digital output driver supply (1.5 V to 3 V) |
| 引脚 3 | D0B-/DNC — Channel B data bit 0 (CMOS mode) / NC in DDR mode |
| 引脚 4 | D1B — Channel B data bit 1 (CMOS mode) / D0B in DDR mode |
| 引脚 5 | D2B — Channel B data bit 2 (CMOS mode) / D1B in DDR mode |
| 引脚 6 | D3B — Channel B data bit 3 (CMOS mode) / D2B in DDR mode |
| 引脚 7 | D4B — Channel B data bit 4 (CMOS mode) / D3B in DDR mode |
| 引脚 8 | D5B — Channel B data bit 5 (CMOS mode) / D4B in DDR mode |
| 引脚 9 | D6B — Channel B data bit 6 (CMOS mode) / D5B in DDR mode |
| 引脚 10 | D7B — Channel B data bit 7 (CMOS mode) / D6B in DDR mode |
| 引脚 11 | D8B — Channel B data bit 8 (CMOS mode) / D7B in DDR mode |
| 引脚 12 | D9B — Channel B data bit 9 (CMOS mode) / D8B in DDR mode |
| 引脚 13 | D10B — Channel B data bit 10 (CMOS mode) / D9B in DDR mode |
| 引脚 14 | D11B — Channel B data bit 11 (CMOS mode) / D10B in DDR mode |
| 引脚 15 | D12B — Channel B data bit 12 (CMOS mode) / D11B in DDR mode |
| 引脚 16 | D13B — Channel B data bit 13 (CMOS mode) / D12B in DDR mode |
| 引脚 17 | NC — Not connected (per datasheet) |
| 引脚 18 | NC — Not connected (per datasheet) |
| 引脚 19 | OGND — Digital output driver ground |
| 引脚 20 | OVDD — Digital output driver supply |
| 引脚 21 | OGND — Digital output driver ground |
| 引脚 22 | OVDD — Digital output driver supply |
| 引脚 23 | CLKOUTB — Channel B clock output (CMOS) |
| 引脚 24 | CLKOUTB+ — Channel B clock output positive (DDR) |
| 引脚 25 | OGND — Digital output driver ground |
| 引脚 26 | OVDD — Digital output driver supply |
| 引脚 27 | CLKOUTA — Channel A clock output (CMOS) |
| 引脚 28 | CLKOUTA+ — Channel A clock output positive (DDR) |
| 引脚 29 | OGND — Digital output driver ground |
| 引脚 30 | OVDD — Digital output driver supply |
| 引脚 31 | D13A — Channel A data bit 13 |
| 引脚 32 | D12A — Channel A data bit 12 |
| 引脚 33 | D11A — Channel A data bit 11 |
| 引脚 34 | D10A — Channel A data bit 10 |
| 引脚 35 | D9A — Channel A data bit 9 |
| 引脚 36 | D8A — Channel A data bit 8 |
| 引脚 37 | OGND — Digital output driver ground |
| 引脚 38 | OVDD — Digital output driver supply |
| 引脚 39 | D7A — Channel A data bit 7 |
| 引脚 40 | D6A — Channel A data bit 6 |
| 引脚 41 | D5A — Channel A data bit 5 |
| 引脚 42 | D4A — Channel A data bit 4 |
| 引脚 43 | D3A — Channel A data bit 3 |
| 引脚 44 | D2A — Channel A data bit 2 |
| 引脚 45 | D1A — Channel A data bit 1 |
| 引脚 46 | D0A-/DNC — Channel A data bit 0 (CMOS) / NC (DDR) |
| 引脚 47 | OGND — Digital output driver ground |
| 引脚 48 | OVDD — Digital output driver supply |
| 引脚 49 | MODE — Mode select (CMOS/DDR, full/complement output) |
| 引脚 50 | OE — Output enable (active high) |
| 引脚 51 | SENSE — Input range select (1 Vp-p or 2 Vp-p) |
| 引脚 52 | VREF — Reference decoupling pin |
| 引脚 53 | REFT — Reference top decoupling |
| 引脚 54 | REFB — Reference bottom decoupling |
| 引脚 55 | AINB- — Channel B analog input negative |
| 引脚 56 | AINB+ — Channel B analog input positive |
| 引脚 57 | AGND — Analog ground |
| 引脚 58 | AVDD — Analog supply (3 V) |
| 引脚 59 | AGND — Analog ground |
| 引脚 60 | AINA+ — Channel A analog input positive |
| 引脚 61 | AINA- — Channel A analog input negative |
| 引脚 62 | CLK — Sample clock input |
| 引脚 63 | CLK — Sample clock input (complementary) |
| 引脚 64 | AGND — Analog ground |
典型应用
LTC2299IUP 适用于 6 应用s: Cellular Baseband Receiver IF Digitizer, Medical Imaging Receiver Front-End, Cable Headend QAM Demodulator, Broadband Spectrum Analyzer ADC, Multi-Channel Data Acquisition System, Phased-Array Radar Digitizer.
Cellular Baseband Receiver IF Digitizer
The LTC2299IUP directly digitizes the IF stage in multi-carrier cellular basestation receivers. The 73 dB SNR and 90 dB SFDR at 70 MHz input satisfy 3GPP spurious-emission masks with 7 to 9 dB margin, and the dual-channel integration captures I and Q paths from a single antenna card, reducing board space by ~30 percent versus two single-channel ADCs.
推荐
Medical Imaging Receiver Front-End
In CT scanner or ultrasound beamformer designs, the LTC2299IUP digitizes two phased-array channels simultaneously at 80 Msps, capturing full-bandwidth pre-beamformed RF with 90 dB SFDR to preserve contrast resolution. The 575 MHz input bandwidth supports Nyquist sampling of intermediate frequencies up to 70 MHz, and the 125 mW power dissipation keeps multi-channel arrays thermally manageable.
推荐
Cable Headend QAM Demodulator
The LTC2299IUP samples downstream QAM carriers up to 1 GHz by undersampling, leveraging its 575 MHz input bandwidth and dual-channel architecture to digitize adjacent upstream and downstream segments on a single chip. With 73 dB SNR the part supports 1024-QAM bit-error-rate targets without external filtering, and the parallel CMOS outputs interface directly to downstream FPGAs implementing QAM symbol recovery.
推荐
Broadband Spectrum Analyzer ADC
The LTC2299IUP's dual 80 Msps converters feed both real and image-reject paths in a swept-spectrum analyzer digital front end. The 90 dB SFDR captures spurs as low as -90 dBFS, exposing low-level harmonics normally hidden by converter distortion. With the internal dither feature enabled (3 dB SFDR improvement per the datasheet), the part can resolve spurious products below the -100 dBc floor in narrow-band measurements.
推荐
Multi-Channel Data Acquisition System
In multi-channel DAQs for vibration analysis or radar beamforming, the LTC2299IUP replaces two single-channel 14-bit ADCs with one dual-channel device that shares clock, reference, and bias networks, cutting part count by 50 percent. Its wide 575 MHz input bandwidth accommodates harmonics above Nyquist, while the 14-bit resolution and 73 dB SNR deliver 11.5 ENOB, sufficient for demanding industrial measurement systems.
推荐
Phased-Array Radar Digitizer
The LTC2299IUP's dual channel integration aligns with the two quadrature channels used per-element in phased-array radar subsystems. At 80 Msps with 73 dB SNR the converter preserves signal integrity across the entire IF range up to 70 MHz, while independent OVDD selection lets the digital side interface directly to low-power FPGAs. The exposed-pad 64-QFN package enables dense board layouts in tightly-packed array modules.
推荐
推荐产品汇总
工程参考数据： LTC2299IUP ——对比、设计指导和合规信息。
选型指南
与替代料对比
| 参数 | 本产品 | LTC2299CUP | LTC2299IUP#PBF | LTC2299IUP#TRPBF | LTC2297IUP | LTC2292CUP |
|---|---|---|---|---|---|---|
| Brand | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices |
| Package | 64-QFN (9x9) with exposed pad | 64-QFN (9x9) - same | 64-QFN (9x9) - same | 64-QFN (9x9) - same | 64-QFN (9x9) - same | 64-QFN (9x9) - same |
| Resolution | 14 bits | 14 bits | 14 bits | 14 bits | 12 bits | 12 bits |
| Sampling Rate | 80 Msps | 80 Msps | 80 Msps | 80 Msps | 80 Msps | 40 Msps |
| Number of Channels | 2 (dual) | 2 (dual) | 2 (dual) | 2 (dual) | 2 (dual) | 2 (dual) |
| Temperature Grade | Industrial (-40C to +85C) | Commercial (0C to +70C) | Industrial (-40C to +85C) | Industrial (-40C to +85C) | Industrial (-40C to +85C) | Commercial (0C to +70C) |
| Finishing / Packaging Code | Tray (no suffix) | Tray | Tray, Pb-free | Tape and reel, Pb-free | Tray | Tray |
关键差异点
- Higher dynamic range at same 80 Msps speed （对比 LTC2297IUP)
- Higher sampling rate than 12-bit predecessor （对比 LTC2292CUP)
- Independent OVDD eliminates level shifters （对比 LTC2299IUP#PBF)
设计说明
The exposed pad (Pin 65 on the QFN thermal pad) is the primary thermal path and the main return for the analog ground reference. Use a continuous ground plane on the top layer stitched under the QFN with a 3x3 (or denser) array of vias connecting to an inner ground plane. Estimated thermal resistance is approximately 30 C/W on a 4-layer 2 oz board - 1.5 W total power dissipation (125 mW internal plus driver overhead) results in roughly 45 C junction-to-ambient temperature rise.
Separate the analog ground (AGND) and digital output ground (OGND) planes. Join them at a single point beneath the exposed pad. Route the analog input traces AINA+/AINA- and AINB+/AINB- as 100-ohm differential pairs and place the input coupling network (typically a 25 ohm resistor and 12 pF capacitor) within 5 mm of the input pins to preserve the 575 MHz analog input bandwidth. Avoid routing digital CMOS outputs across the analog input region.
Estimated: clock jitter of 1 ps RMS at 80 Msps keeps the SNR contribution below the part's 73 dB noise floor. Source the CLK pin from a low-jitter clock generator (e.g., AD9516 or AD9523) using an LVDS or PECL driver, terminated with 100 ohms across the CLK+/CLK- pair. Provide a clean 3V supply to AVDD with a local 10 uF and 0.1 uF ceramic bypass to AGND, located within 3 mm of the supply pin.
Do not load AVDD with a switching regulator output filter directly; route the 3V analog supply through an LDO or ferrite to isolate switching noise. Ensure the SENSE pin is tied to AVSS (1 Vp-p input) or to AVDD (2 Vp-p input) according to the desired full-scale range. Tie unused data pins (NC pins 17 and 18) to OGND rather than leaving them floating to avoid coupling that can degrade channel-to-channel isolation.
合规信息
RoHS/REACH compliant per PBF suffix designation. AEC-Q100 is not applicable - this is an industrial-grade mixed-signal ADC rather than an automotive-qualified part.
