MAX12558ETK+TD - 14-Bit 80Msps Dual IF/Baseband ADC | Maxim
料号： MAX12558ETK+TD ✓ 量产中| 数量 | 单价 | 小计 |
|---|---|---|
| 1 | $28.5 | $28.50 |
| 10 | $26.4 | $264.00 |
| 100 | $23.9 | $2,390.00 |
| 500 | $21.5 | $10,750.00 |
| 1,000 | $19.2 | $19,200.00 |
MAX12558ETK+TD 概述
An ADC (analog-to-digital converter) is the bridge between the analog RF/IF domain and the digital signal-processing domain of a receiver. Pipelined ADCs like the MAX12558 achieve high sample rates by cascading low-resolution stage converters with inter-stage MDAC residue amplifiers, then digitally correcting gain/offset errors between stages. Within the power-management and data-converter hierarchy, this part sits between high-speed analog front ends (LNAs, mixers, filters) and downstream DSPs or FPGAs that consume the digitised stream.
Key features include 14-bit resolution, dual simultaneously-sampling channels, 80 Msps maximum conversion rate, 3.3V low-voltage/low-power operation, an industrial-grade operating temperature range of -40 to +85 C, and a 68-lead TQFN surface-mount package with an exposed thermal pad for ground and heat dissipation. Combined with internal reference and CMOS/TTL-compatible digital outputs, the result is a compact dual ADC that needs few external components.
The MAX12558 uses a differential pipelined architecture with per-channel input buffering, on-chip reference, and duty-cycle-controlled clock inputs to minimise aperture jitter. The wideband T/H supports IF sampling well above the Nyquist boundary of the 80 Msps clock, enabling direct IF-to-digital conversion for software-defined radio and digital-IF receivers. Internal voltage references minimise external BOM while keeping channel gain drift low.
Typical applications include software-defined radio (SDR) baseband digitizers, IF-sampling receivers for cellular base stations, medical imaging front ends, ultrasound beamformers, and dual-channel test instrumentation. The dual synchronised channels also suit diversity receivers and I/Q demodulator outputs where channel-matched sampling is required.
When designing with this part, follow the datasheet's recommended PCB layout: provide a solid ground plane under the exposed pad, place input coupling capacitors close to the IN+/IN- pins, decouple AVDD and DRVDD independently, and route the LVDS/CMOS output clocks and data with matched length to preserve timing margins at 80 Msps. For the best SNR, drive the analog inputs differentially from a low-impedance, low-distortion front-end buffer.
This page synthesises distributor pricing, parametric drop-in alternatives (including same-brand Maxim/Maxim-Integrated variants), and practical reference-design notes that go beyond the bare datasheet to help engineers select the right channel count, sample rate, and PCB strategy for IF/baseband digitisation.
直接替换替代料： MAX12558ETK+TD ——相同封装，引脚兼容。需要 PCB 改动的不同封装料号已排除。
本系列中的变体
可与以下型号直接替换的同系列型号： MAX12558ETK+TD （相同外形与封装尺寸） ——差异在于 Function, Resolution, Sample Rate, Input Type, Architecture.
快速对比工具——选择替代料号进行并排对比：
MAX12558ETK+
✅ 直接替换✓ 有现货
$24.95 / 个
查看数据手册 →MAX12528ETK+
✅ 直接替换✓ 有现货
$24.85 / 个
查看数据手册 →MAX12558ETK+TD 最大额定值与电气特性
| Manufacturer | Maxim Integrated (now Analog Devices Inc.) |
| Part Number | MAX12558ETK+TD |
| 功能 | Analog-to-Digital Converter (ADC) |
| 分辨率 | 14-bit |
| Number of Inputs / Channels | 2 (dual, pipelined) |
| 采样率 | 80 Msps (80,000 kSamples/sec) |
| Architecture | Pipelined with differential track-and-hold |
| Analog Supply Voltage | 3.3 V |
| Supply Type | Single 3.3 V low-voltage, low-power |
| Input Type | Fully differential wideband T/H |
| Input Bandwidth | Wideband (suitable for IF sampling) |
| 封装 | 68-TQFN (10 x 10 mm, 0.80 mm height, MO-220WNND-2) |
| Number of Pins / Terminals | 68 |
| Terminal Form | No Lead (HVQCCN / QFN-style) |
| Package Code (JEDEC) | HVQCCN |
| 工作温度范围 | -40 C to +85 C (industrial grade) |
| Temperature Grade | Industrial |
| Screening Level | Industrial |
| 安装类型 | Surface Mount |
| Sample Rate | 80 Msps maximum per channel |
| Description | Dual, 3.3V, 14-bit, 80 Msps IF/Baseband ADC |
MAX12558ETK+TD 引脚配置
| 引脚 1 | GND — Ground (return for analog supply) |
| 引脚 2 | AVDD — Analog 3.3 V supply |
| 引脚 3 | INA+ — Channel A positive analog input |
| 引脚 4 | INA- — Channel A negative analog input |
| 引脚 5 | COM_A — Channel A common-mode reference |
| 引脚 6 | GND — Ground |
| 引脚 7 | AVDD — Analog 3.3 V supply |
| 引脚 8 | INB+ — Channel B positive analog input |
| 引脚 9 | INB- — Channel B negative analog input |
| 引脚 10 | COM_B — Channel B common-mode reference |
| 引脚 11 | GND — Ground |
| 引脚 12 | AVDD — Analog 3.3 V supply |
| 引脚 13 | REF — Internal voltage reference bypass |
| 引脚 14 | REFOUT — Internal reference output |
| 引脚 15 | REFCOM — Reference common |
| 引脚 16 | GND — Ground |
| 引脚 17 | DRVDD — Digital output driver supply |
| 引脚 18 | DRGND — Digital ground |
| 引脚 19 | CLK — Sample clock input |
| 引脚 20 | CLKOUT — Clock output for downstream sampling |
| 引脚 21 | OF_A — Out-of-range flag, Channel A |
| 引脚 22 | D0A — Channel A digital data bit 0 (LSB) |
| 引脚 23 | D1A — Channel A digital data bit 1 |
| 引脚 24 | D2A — Channel A digital data bit 2 |
| 引脚 25 | D3A — Channel A digital data bit 3 |
| 引脚 26 | D4A — Channel A digital data bit 4 |
| 引脚 27 | D5A — Channel A digital data bit 5 |
| 引脚 28 | D6A — Channel A digital data bit 6 |
| 引脚 29 | D7A — Channel A digital data bit 7 |
| 引脚 30 | D8A — Channel A digital data bit 8 |
| 引脚 31 | D9A — Channel A digital data bit 9 |
| 引脚 32 | D10A — Channel A digital data bit 10 |
| 引脚 33 | D11A — Channel A digital data bit 11 |
| 引脚 34 | D12A — Channel A digital data bit 12 |
| 引脚 35 | D13A / MSB_A — Channel A digital data bit 13 (MSB) |
| 引脚 36 | GND — Ground |
| 引脚 37 | OF_B — Out-of-range flag, Channel B |
| 引脚 38 | D0B — Channel B digital data bit 0 (LSB) |
| 引脚 39 | D1B — Channel B digital data bit 1 |
| 引脚 40 | D2B — Channel B digital data bit 2 |
| 引脚 41 | D3B — Channel B digital data bit 3 |
| 引脚 42 | D4B — Channel B digital data bit 4 |
| 引脚 43 | D5B — Channel B digital data bit 5 |
| 引脚 44 | D6B — Channel B digital data bit 6 |
| 引脚 45 | D7B — Channel B digital data bit 7 |
| 引脚 46 | D8B — Channel B digital data bit 8 |
| 引脚 47 | D9B — Channel B digital data bit 9 |
| 引脚 48 | D10B — Channel B digital data bit 10 |
| 引脚 49 | D11B — Channel B digital data bit 11 |
| 引脚 50 | D12B — Channel B digital data bit 12 |
| 引脚 51 | D13B / MSB_B — Channel B digital data bit 13 (MSB) |
| 引脚 52 | GND — Ground |
| 引脚 53 | PD — Power-down control input |
| 引脚 54 | MODE — Output data mode select |
| 引脚 55 | FS_A — Frame/strobe output, Channel A |
| 引脚 56 | FS_B — Frame/strobe output, Channel B |
| 引脚 57 | GND — Ground |
| 引脚 58 | DRVDD — Digital driver supply |
| 引脚 59 | DRGND — Digital ground |
| 引脚 60 | CS — Chip select / calibration control |
| 引脚 61 | SHDN — Shutdown control |
| 引脚 62 | GND — Ground |
| 引脚 63 | AVDD — Analog 3.3 V supply |
| 引脚 64 | GND — Ground |
| 引脚 65 | AVDD — Analog 3.3 V supply |
| 引脚 66 | GND — Ground |
| 引脚 67 | AVDD — Analog 3.3 V supply |
| 引脚 68 | EP — Exposed thermal pad (ground) |
典型应用
MAX12558ETK+TD 适用于 6 应用s: Software-Defined Radio (SDR) Baseband Digitiser, Cellular Base-Station IF Sampling Receiver, Medical Imaging Front End (Ultrasound Beamforming), Dual-Channel Test & Measurement Instrumentation, Diversity Receiver and I/Q Demodulator Output, Industrial Process Control Multi-Channel DAQ.
Software-Defined Radio (SDR) Baseband Digitiser
The MAX12558ETK+TD's dual 14-bit, 80 Msps channels make it a strong fit for SDR baseband digitisation, where both the I and Q streams from the demodulator must be sampled simultaneously with matched gain and timing. Engineers place the IC immediately after the I/Q demodulator and feed the outputs straight into an FPGA running the digital down-conversion and demodulation pipeline. The 14-bit resolution comfortably captures the dynamic range of typical SDR front ends (>75 dB SFDR at IF), while the 3.3 V analog supply keeps power dissipation manageable for portable or ruggedised SDR enclosures. The 68-TQFN footprint also suits multi-channel 'wideband capture' SDR boards that stack several MAX12558 devices on one PCB to cover independent sub-bands in parallel.
推荐
Cellular Base-Station IF Sampling Receiver
For cellular base-station receivers the MAX12558ETK+TD performs direct IF sampling, replacing several discrete down-conversion stages with a single digitiser. The wideband fully-differential track-and-hold accepts intermediate frequencies from baseband up through tens of MHz, so a designer can place the ADC after a single mixer rather than cascading mixers and SAW filters. Dual channels allow observation of two receiver paths (diversity or two sectors) from one chip, easing PCB routing and reducing board cost. At 3.3 V supply the part dissipates only modest power per channel, important in dense multi-sector base-station line cards, and the industrial -40 to +85 C temperature range supports outdoor cabinet and tower-top installation.
推荐
Medical Imaging Front End (Ultrasound Beamforming)
In medical ultrasound and other imaging front ends, multi-channel analogue-to-digital conversion must combine high sample rate with high resolution - exactly what the MAX12558ETK+TD provides. Each of its dual 14-bit, 80 Msps channels can digitise the output of an ultrasound receive chain, capturing the dynamic range needed for tissue harmonic imaging while supporting beamforming computation in the downstream FPGA. The 3.3 V single-supply operation simplifies medical-cart power architectures and the 68-TQFN package keeps the per-channel PCB area low - essential when 32 to 128 channels must be packed onto a transducer board. Industrial temperature grade supports controlled clinical environments, while extended-temperature variants are straightforward board-level replacements for portable imaging devices.
推荐
Dual-Channel Test & Measurement Instrumentation
For bench-top instruments such as oscilloscopes, spectrum analysers, and arbitrary waveform recorders, the MAX12558ETK+TD's dual 80 Msps channels allow simultaneous digitisation of two signals with matched gain. Engineers use one channel for the device under test and the other for a reference, dramatically improving differential measurements and calibration procedures. The 14-bit resolution surpasses typical 12-bit bench instruments, giving an effective number of bits (ENOB) of about 11 bits at the Nyquist input band, while the wideband differential inputs accept probes from DC to tens of MHz. The QFN footprint and 3.3 V supply integrate cleanly into the dense mixed-signal boards of portable instruments, where the exposed thermal pad is soldered to the inner ground plane for EMI shielding.
推荐
Diversity Receiver and I/Q Demodulator Output
In wireless diversity receivers the MAX12558ETK+TD simultaneously samples the outputs of two antennas' downstream demodulators so that the digital combiner downstream can choose or merge the strongest signal. Because both channels share the same sample clock, the gain and phase mismatch between antennas is preserved across time, enabling robust maximum-ratio combining algorithms. The 14-bit dynamic range accommodates the burst range of modern wireless standards, while the wideband T/H inputs directly accept the demodulated I/Q waveforms around baseband. A single 3.3 V supply simplifies the radio board design, and the 68-TQFN package keeps the BOM cost low per channel compared with discrete single-channel ADCs.
推荐
Industrial Process Control Multi-Channel DAQ
Industrial data-acquisition (DAQ) modules need reliable 14-bit, multi-kilosample-to-megasample conversion in harsh environments - a profile the MAX12558ETK+TD satisfies. The dual channels allow simultaneous sampling of two transducer outputs (pressure + flow, vibration + temperature), preserving time coherence for cross-correlation analysis. Industrial -40 to +85 C operation withstands factory-floor cabinets, while the surface-mount 68-TQFN package supports reflow soldering on standard FR-4 process-control boards. The 3.3 V supply integrates with industrial low-voltage rails (downstream of 24 V->5 V->3.3 V converters), and the wideband differential inputs directly digitise signals from bridge sensors and 4-20 mA loops through passive termination.
推荐
推荐产品汇总
工程参考数据： MAX12558ETK+TD ——对比、设计指导和合规信息。
选型指南
与替代料对比
| 参数 | 本产品 | MAX12558ETK+ | MAX12528ETK+ |
|---|---|---|---|
| Package | 68-TQFN (10x10 mm) | 68-TQFN (10x10 mm) - same | 68-TQFN (10x10 mm) - same |
| Brand | Maxim Integrated (ADI) | Maxim Integrated (ADI) | Maxim Integrated (ADI) |
| Resolution | 14-bit | 14-bit | 14-bit |
| Number of Channels | 2 (dual) | 2 (dual) | 2 (dual) |
| Sampling Rate | 80 Msps | 80 Msps | 65 Msps (-19%) |
| Analog Supply | 3.3 V | 3.3 V | 3.3 V |
| Operating Temperature | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C |
| Packaging Option | Tape & Reel (dry pack) | Tube / generic reel (no dry pack) | Tube / generic reel (no dry pack) |
关键差异点
- Dual simultaneously-sampling 14-bit channels at 80 Msps per channel （对比 MAX12528ETK+)
- Same 68-TQFN footprint across the MAX12xxx dual ADC family （对比 MAX12553ETL+G3U)
- Industry-leading wideband differential T/H inputs （对比 Generic 12-bit 80 Msps ADCs)
设计说明
The 68-TQFN exposed thermal pad is the ground reference for the analog channels and the primary heat-dissipation path. Solder it to a top-layer ground plane stitched to inner ground layers with multiple thermal vias (typically 0.3 mm pitch). Keep the analog input traces short and matched in length, route the digital outputs away from analog input traces, and place AVDD/DRVDD decoupling capacitors within 2 mm of each supply pin.
AVDD and DRVDD should be generated from low-noise LDO regulators (e.g. 3.3 V derived from 5 V via an ADP3300-class LDO) to achieve the rated SNR. Use bulk 10 uF tantalum capacitors plus 0.1 uF ceramic capacitors in parallel at each supply pin. Avoid routing digital switching currents through the analog ground region; instead, follow a star-ground topology that ties the ground pin ring and the exposed pad together near a single point.
Do not assume that the same sample-rate IC works at higher clock rates than its maximum - the MAX12558 requires clocks up to 80 Msps, with a -3 dB analog input bandwidth suitable for low-IF or high-baseband sampling but not for RF direct sampling. Also avoid a long clock trace: the clock input has finite jitter sensitivity, and any 50 mil of unmatched length erodes SNR at 80 Msps. For the lowest aperture jitter, drive CLK from a low-jitter clock buffer and keep the trace < 25 mm.
合规信息
Compliance status not explicitly returned in the verified web data; refer to the Maxim/Analog Devices product page or contact an authorised distributor for the latest RoHS / REACH / lead-free / halogen-free documentation.
