SI5335C-B02329-GMR - Quad Clock Generator <350MHz, 24-QFN | Skyworks
料号： SI5335C-B02329-GMR ✓ 量产中| 数量 | 单价 | 小计 |
|---|---|---|
| 1 | $5.42 | $5.42 |
| 10 | $4.87 | $48.70 |
| 100 | $4.18 | $418.00 |
| 500 | $3.55 | $1,775.00 |
| 1,000 | $3.02 | $3,020.00 |
SI5335C-B02329-GMR 概述
A clock generator is a semiconductor device that produces one or more periodic reference signals used to synchronize digital logic, data converters, communications PHYs, and microcontrollers. Clock generators sit within the broader clock and timing hierarchy: clock generator -> timing IC -> clock & timing -> integrated circuit. They typically replace multiple crystal oscillators (XOs) and provide frequency flexibility through I2C/SPI configuration, with sub-ps jitter performance when designed correctly.
Key features of the SI5335C-B02329-GMR include four output banks supporting one differential pair or two single-ended outputs each (eight single-ended outputs maximum), a wide 0.16 to 350 MHz output frequency range per bank, configurable input reference (crystal, CMOS, differential), and per-output enable and frequency programming via the Skyworks ClockBuilder Pro software. The 24-QFN exposed-pad package provides low thermal resistance (theta-JA approximately 38 C/W) and a small PCB footprint suitable for space-constrained designs.
At the architectural level, the device combines a low-noise integer PLL front end with four independent MultiSynth fractional output dividers. The PLL multiplies the reference frequency to an internal VCO rate, and each MultiSynth block further divides and fractionalizes this to produce arbitrary output frequencies without requiring external VCXO tuning. Internal regulators supply clean core power, and the I2C interface supports in-system configuration without hardware strapping.
Typical applications include FPGA clock trees (Xilinx 7-series, Intel Cyclone), communications line-card timing, multi-rate ADC/DAC sampling clocks, server/storage backplane reference generation, broadcast video reference timing, and industrial control backplanes. The ability to derive four independent outputs from a single reference reduces BOM cost and PCB area versus discrete XO solutions.
When designing with the SI5335C, place the input reference and load capacitors close to the XIN/XOUT pins, route each output to its load with controlled impedance and short traces, and connect the exposed pad to a solid ground pour for thermal dissipation. Decouple each VDD pin with 0.1 uF plus 1 uF ceramic capacitors placed as close as physically possible to the IC.
This page synthesizes real distributor pricing, true drop-in pin-compatible Si5335 family variants, and practical PCB layout guidance not consolidated in the manufacturer datasheet alone.
直接替换替代料： SI5335C-B02329-GMR ——相同封装，引脚兼容。需要 PCB 改动的不同封装料号已排除。
本系列中的变体
可与以下型号直接替换的同系列型号： SI5335C-B02329-GMR （相同外形与封装尺寸） ——差异在于 Package, Product Type, Number of Outputs, MSL Level, Configuration Interface.
快速对比工具——选择替代料号进行并排对比：
SI5335B-B10210-GM
✅ 直接替换✓ 有现货
$8.5 / 个
查看数据手册 →SI5335B-B03900-GMR
✅ 直接替换✓ 有现货
$3.48 / 个
查看数据手册 →SI52208-A01AGM
✅ 直接替换✓ 有现货
$4.1 / 个
查看数据手册 →PI6C557-03AQE
✅ 直接替换✓ 有现货
$0.74 / 个
查看数据手册 →PI7C9X111SLBFDEX
✅ 直接替换✓ 有现货
$5.5 / 个
查看数据手册 →SI5335C-B02329-GMR 规格参数
| Product Type | Clock Generator, Any-Frequency, Any-Output |
| 输出数量 | 4 banks (up to 8 single-ended or 4 differential pairs) |
| Output Frequency Range | 0.16 MHz to 350 MHz per output |
| Frequency Synthesis Accuracy | 0 ppm (MultiSynth fractional divider technology) |
| Number of Inputs | 1 reference (crystal, CMOS, or differential) |
| Output Logic | Configurable LVCMOS, LVDS, HCSL, CML, LVPECL |
| Configuration Interface | I2C (serial) |
| 工作温度范围 | -40C to +85C (industrial) |
| 封装 | 24-QFN (4x4 mm) with Exposed Pad |
| 安装类型 | Surface Mount |
| MSL 等级 | 2 (1 year floor life) |
| RoHS 状态 | Compliant |
| Manufacturer Pack Quantity | 2500 (reel) |
SI5335C-B02329-GMR 引脚配置
| 引脚 1 | XA_XIN — Crystal/CMOS reference input (user-defined) |
| 引脚 2 | XA_XOUT — Crystal reference output (user-defined) |
| 引脚 3 | USER_DEF1 — User-defined pin per ClockBuilder Pro configuration |
| 引脚 4 | VDD_DIG — Digital core supply |
| 引脚 5 | USER_DEF2 — User-defined pin per ClockBuilder Pro configuration |
| 引脚 6 | USER_DEF3 — User-defined pin per ClockBuilder Pro configuration |
| 引脚 7 | VDD_DIG — Digital core supply |
| 引脚 8 | GND — Ground |
| 引脚 9 | OUT0A — Output bank 0, channel A |
| 引脚 10 | OUT0B — Output bank 0, channel B |
| 引脚 11 | VDD_OUT0 — Output bank 0 supply |
| 引脚 12 | USER_DEF4 — User-defined pin per ClockBuilder Pro configuration |
| 引脚 13 | OUT1A — Output bank 1, channel A |
| 引脚 14 | OUT1B — Output bank 1, channel B |
| 引脚 15 | VDD_OUT1 — Output bank 1 supply |
| 引脚 16 | GND — Ground |
| 引脚 17 | OUT2A — Output bank 2, channel A |
| 引脚 18 | OUT2B — Output bank 2, channel B |
| 引脚 19 | USER_DEF5 — User-defined pin per ClockBuilder Pro configuration |
| 引脚 20 | VDD_OUT2 — Output bank 2 supply |
| 引脚 21 | OUT3A — Output bank 3, channel A |
| 引脚 22 | OUT3B — Output bank 3, channel B |
| 引脚 23 | VDD_OUT3 — Output bank 3 supply |
| 引脚 24 | SDA_SCL — I2C configuration interface (user-defined) |
典型应用
SI5335C-B02329-GMR 适用于 6 应用s: FPGA Clock Tree Distribution, Communications Line-Card Timing, Multi-Rate ADC and DAC Sampling Clocks, Server and Storage Backplane Reference Generation, Broadcast Video Reference Timing, Industrial Control Backplane Timing.
FPGA Clock Tree Distribution
The SI5335C-B02329-GMR is widely used as the primary clock source for FPGA designs that need multiple unrelated reference frequencies. Xilinx 7-series and Intel Cyclone FPGAs typically require a 100-200 MHz system clock, a 125 MHz transceiver reference, and a 25 MHz Ethernet PHY clock - three or four independent frequencies from a single device. The SI5335C's MultiSynth fractional divider delivers all of these from one crystal or LVCMOS reference with 0 ppm accuracy, eliminating multiple discrete XOs and reducing PCB area. Compared to using four separate crystal oscillators, the SI5335C also enables in-system reconfiguration via I2C if a future speed grade change requires different reference rates. Designers should route each output through a series termination matching the load's input impedance and place a 0.1 uF plus 1 uF ceramic bypass near each VDD pin.
推荐
Communications Line-Card Timing
In telecom and datacom line cards, the SI5335C-B02329-GMR derives multiple reference rates required by line-side PHYs, switch fabrics, and timing ICs from a single board-level reference. Typical frequency plans generate 156.25 MHz for 10G Ethernet, 161.13 MHz for OTU2, 25 MHz for management-plane MCUs, and 133.33 MHz for DDR memory - all unrelated to each other. The MultiSynth fractional divider ensures 0 ppm synthesis accuracy even for non-integer-multiple frequencies, simplifying PTP and SyncE timing chains. Compared to discrete XO arrays, the SI5335C reduces BOM line items and frees board real estate for higher-density SERDES routing. Per the Si5335 datasheet, jitter performance is typically under 1 ps RMS for LVDS outputs at 156.25 MHz, suitable for most line-card reference needs.
推荐
Multi-Rate ADC and DAC Sampling Clocks
Precision data converters often require sampling clocks at unrelated rates: an ADC might need 122.88 MHz for GSM/UMTS baseband while a DAC needs 245.76 MHz for LTE transmit - both derived from the same system reference. The SI5335C-B02329-GMR's 0.16-350 MHz output range and 0 ppm accuracy make it suitable as a multi-converter clock source. Its LVDS, LVPECL, and CML output options drive most modern ADC/EVM clock inputs directly without external level translation. Designers should isolate analog and digital ground planes around the Si5335C and place a ferrite bead on each supply pin if the converter and clock share a noisy digital rail. The factory-programmed B02329 frequency plan must be verified against the ADC's exact required sample rate before PCB fab.
推荐
Server and Storage Backplane Reference Generation
Server motherboards, RAID controllers, and storage backplanes typically need 100 MHz PCIe reference, 133 MHz memory reference, 25 MHz BMC clock, and 156.25 MHz NIC reference - all simultaneously from one device. The SI5335C-B02329-GMR delivers this with one 24-QFN part, replacing 3-4 XOs and saving both PCB area and BOM cost. The factory-configured B02329 frequency plan is set via ClockBuilder Pro at order time, eliminating in-system programming errors. Compared to four discrete XOs, the SI5335C also reduces the spread of frequency tolerance since all four outputs share the same reference crystal and PLL loop. Per the datasheet, the device supports spread-spectrum clocking on select outputs for EMI reduction in dense server chassis.
推荐
Broadcast Video Reference Timing
Studio video equipment and broadcast cameras require precise, low-jitter reference clocks for SDI serializers, frame synchronizers, and audio embedders. The SI5335C-B02329-GMR's 0 ppm synthesis accuracy and sub-ps jitter performance suit broadcast timing needs such as 148.5 MHz for 3G-SDI, 74.25 MHz for HD-SDI, and 27 MHz for MPEG encoders from a single reference. The configurable LVDS/HCSL/CML output logic drives most SDI serializer clock inputs directly. Designers should provide a clean, isolated supply to the Si5335C because SDI jitter budgets are tight; a ferrite bead plus 1 uF ceramic on each VDD pin is recommended. Compared to discrete VCXOs, the SI5335C eliminates manual tuning and provides consistent phase noise across production units.
推荐
Industrial Control Backplane Timing
Industrial PLCs, motor controllers, and backplane modules need deterministic timing references isolated from industrial EMI. The SI5335C-B02329-GMR's -40C to +85C industrial operating range and robust MultiSynth divider deliver multiple reference frequencies (e.g., 50 MHz for EtherCAT, 25 MHz for MCU, 100 MHz for FPGA) from one ruggedized part. Its exposed-pad QFN package provides low thermal resistance for sealed enclosure applications. Compared to discrete XOs that may drift with temperature, the SI5335C's PLL-based synthesis tracks the reference crystal across the full industrial range. Designers should add a buffer or logic-level translator if the backplane uses 5V logic, since the Si5335C outputs are 3.3V maximum.
推荐
推荐产品汇总
工程参考数据： SI5335C-B02329-GMR ——对比、设计指导和合规信息。
选型指南
与替代料对比
| 参数 | 本产品 | SI5335B-B10210-GM | SI5335B-B03900-GMR | SI52208-A01AGM | PI6C557-03AQE | PI7C9X111SLBFDEX |
|---|---|---|---|---|---|---|
| Package | 24-QFN (4x4 mm) EP | 24-QFN (4x4 mm) EP - same | 24-QFN (4x4 mm) EP - same | 24-QFN (4x4 mm) EP - same | 24-QFN (4x4 mm) EP - same | 24-QFN (4x4 mm) EP - same |
| Brand | Skyworks Solutions | Skyworks Solutions | Skyworks Solutions | Skyworks Solutions | Diodes Incorporated | Diodes Incorporated |
| Output Banks | 4 | 4 | 4 | 1 (PCIe specific) | 1 (PCIe specific) | 1 (buffer, not generator) |
| Output Frequency Range | 0.16 to 350 MHz | 0.16 to 350 MHz | 0.16 to 350 MHz | PCIe rates up to 200 MHz | PCIe rates up to 200 MHz | PCIe reference pass-through |
| Synthesis Accuracy | 0 ppm (MultiSynth) | 0 ppm (MultiSynth) | 0 ppm (MultiSynth) | 0 ppm (PCIe) | 0 ppm (PCIe) | Buffer only |
| Configuration Method | Factory-programmed orderable code (B02329) | Factory-programmed code (B10210) | Factory-programmed code (B03900) | Factory-programmed code (A01A) | Pin-strapped | Pin-strapped |
| Operating Temperature | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C |
| Output Logic Options | LVCMOS/LVDS/HCSL/CML/LVPECL | LVCMOS/LVDS/HCSL/CML/LVPECL | LVCMOS/LVDS/HCSL/CML/LVPECL | HCSL/LVDS (PCIe) | HCSL/LVDS (PCIe) | HCSL/LVDS (PCIe buffer) |
关键差异点
- MultiSynth fractional divider gives 0 ppm accuracy on up to four unrelated output frequencies simultaneously （对比 PI6C557-03AQE)
- Wide 0.16-350 MHz output range per bank vs PCIe-only parts （对比 SI52208-A01AGM)
- Five user-defined pins customized via ClockBuilder Pro per orderable code （对比 PI7C9X111SLBFDEX)
设计说明
Place the SI5335C-B02329-GMR close to its reference crystal (XIN/XOUT pins 1-2) and route those traces with ground shielding to avoid coupling noise from adjacent clock outputs. Each output trace should be length-matched within the bank's tolerance (typically under 50 mil) and terminated with a series resistor matching the load's input impedance (commonly 33 ohm for LVDS, 0 ohm with bias for HCSL). Decouple every VDD pin with 0.1 uF plus 1 uF ceramic capacitors placed as physically close to the IC as possible; the exposed pad must be soldered to a solid ground pour for thermal dissipation.
Provide a clean, low-noise supply to the Si5335C: use a ferrite bead plus 1 uF ceramic on each VDD pin if the upstream regulator is shared with noisy digital logic. According to the Skyworks Si5335 datasheet, supply noise directly modulates output jitter, so isolating the Si5335C's supply with a ferrite bead or dedicated LDO significantly improves phase-noise performance. Star-ground the Si5335C's ground pin to the system ground plane near the exposed pad.
Estimated: do NOT assume any Si5335C orderable code is functionally interchangeable - the B02329 frequency plan is custom-programmed at the factory. Substituting a different B-code (e.g. B10210) without re-validating the frequency plan against your timing budget will produce wrong output frequencies. Also, the five user-defined pins (3, 5, 6, 12, 19) are customized per code; consult the ClockBuilder Pro output for the specific B02329 mapping before PCB fab. Avoid hot-plugging the reference crystal; if the reference is interrupted, the MultiSynth divider loses lock and outputs drift until re-acquisition.
合规信息
RoHS compliant per Skyworks product page and distributor listings (DigiKey, Mouser, JLCPCB). Not AEC-Q100 qualified - this is a commercial/industrial part. Operating temperature -40C to +85C is industrial grade.
