TPS53622RSBT - VR13 Dual-Channel D-CAP+ Controller | TI
料号： TPS53622RSBT ✓ 量产中| 数量 | 单价 | 小计 |
|---|---|---|
| 1 | $7.2 | $7.20 |
| 10 | $6.48 | $64.80 |
| 100 | $5.42 | $542.00 |
| 500 | $4.68 | $2,340.00 |
| 1,000 | $3.96 | $3,960.00 |
TPS53622RSBT 概述
A step-down controller is a power management IC that generates a regulated output voltage lower than its input by driving external power stage MOSFETs. It sits in the voltage regulator hierarchy as the control brain of a multiphase buck converter, converting the 12V server bus into low-voltage core, I/O, and memory rails. The TPS53622 uses D-CAP+ architecture with undershoot reduction (USR), delivering fast transient response, low output capacitance, and good current sharing without external loop compensation.
Key features include dual-channel operation in 2+0/1+1 phase configurations, built-in NVM for storing configuration settings, and a PMBus interface for telemetry and control. The controller is fully compatible with TI NexFET power stages such as the CSD95490Q5MC, enabling high-efficiency, highly integrated power conversion solutions with minimal external component count.
The TPS53622 integrates SVID logic, allowing direct communication with Intel VR13 processors. Its D-CAP+ control loop provides excellent load transient performance, critical for modern CPUs with rapidly changing current demands. NVM storage reduces boot time and ensures consistent behavior across power cycles, while PMBus enables real-time monitoring of voltage and current for system optimization.
Typical applications include server VCCIO and VMCP rails, high-performance computing, data center power delivery, and storage systems. A TI reference design demonstrates 12V input to 1V output at 40A using two CSD95490Q5MC power stages.
When designing with the TPS53622, ensure proper layout of the power stage and decoupling capacitors to minimize parasitic inductance, and follow TI's VR13 reference designs for SVID timing compliance.
直接替换替代料： TPS53622RSBT ——相同封装，引脚兼容。需要 PCB 改动的不同封装料号已排除。
本系列中的变体
可与以下型号直接替换的同系列型号： TPS53622RSBT （相同外形与封装尺寸） ——差异在于 Package, Topology, Output Voltage Range, Control Architecture, Function.
快速对比工具——选择替代料号进行并排对比：
TPS53624
✅ 直接替换✓ 有现货
$1.86 / 个
查看数据手册 →TPS53632GRSMT
✅ 直接替换 ⚠️ 规格未核验✓ 有现货
$5.1 / 个
查看数据手册 →TPS536C9T
⚡ 相同封装 ⚠️ 规格未核验✓ 有现货
$5.8 / 个
查看数据手册 →TPS53315
⚡ 相同封装 ⚠️ 规格未核验✓ 有现货
$3.52 / 个
查看数据手册 →TPS53915RVER
⚡ 相同封装 ⚠️ 规格未核验✓ 有现货
$3.48 / 个
查看数据手册 →TPS53622RSBT 最大额定值与电气特性
| 功能 | Step-Down Multiphase Controller |
| 拓扑 | D-CAP+ with Undershoot Reduction (USR) |
| 输出数量 | 2 |
| Phase Configuration | 2+0 or 1+1 |
| Protocol | Intel VR13 SVID, PMBus |
| Non-Volatile Memory | Yes (built-in NVM) |
| Power Stage Compatibility | TI NexFET power stages |
| Applications | Server VCCIO + VMCP rails |
| 封装 | 40-WQFN (5x5 mm) with exposed pad |
| 工作温度 | -40C to +125C |
| 安装类型 | Surface Mount |
| RoHS 状态 | Compliant |
TPS53622RSBT 引脚配置
| 引脚 1 | [DATA_NEEDED] — Pinout requires the TI TPS53622 datasheet pin map (40-pin WQFN) |
| 引脚 2 | [DATA_NEEDED] — [DATA_NEEDED] |
| 引脚 3 | [DATA_NEEDED] — [DATA_NEEDED] |
| 引脚 4 | [DATA_NEEDED] — [DATA_NEEDED] |
| 引脚 5 | [DATA_NEEDED] — [DATA_NEEDED] |
| 引脚 6 | [DATA_NEEDED] — [DATA_NEEDED] |
| 引脚 7 | [DATA_NEEDED] — [DATA_NEEDED] |
| 引脚 8 | [DATA_NEEDED] — [DATA_NEEDED] |
| 引脚 9 | [DATA_NEEDED] — [DATA_NEEDED] |
| 引脚 10 | [DATA_NEEDED] — [DATA_NEEDED] |
典型应用
TPS53622RSBT 适用于 6 应用s: Server VCCIO Rail, Server VMCP / Memory Rail, High-Performance Computing Power Delivery, Data Center 12V Bus Conversion, Storage System Power Management, VR13 Reference Design Reuse.
Server VCCIO Rail
The TPS53622's VR13 SVID compliance makes it a primary choice for Intel server VCCIO power delivery. One channel can be configured as a 2-phase rail using D-CAP+ with undershoot reduction (USR), delivering the fast transient response required when the CPU switches between load states. Paired with TI NexFET power stages such as the CSD95490Q5MC, the complete solution achieves high efficiency at 12V input with minimal external components. NVM stores the rail configuration so the controller boots correctly before SVID communication, while PMBus provides voltage telemetry for platform health monitoring in data center deployments.
推荐
Server VMCP / Memory Rail
The second channel of the TPS53622 serves VMCP and memory power rails in VR13 server platforms, operating as a 1-phase output alongside the VCCIO channel. The D-CAP+ architecture provides good current sharing and low output capacitance, reducing BOM cost on memory rails where voltage accuracy and ripple matter for DRAM reliability. PMBus telemetry enables the BMC to monitor rail health continuously. Because both channels share one controller, the solution reduces board area and sequencing complexity compared to discrete controllers, and the 5x5 mm WQFN package fits dense server VR layouts.
推荐
High-Performance Computing Power Delivery
For HPC accelerator and compute boards that follow Intel VR13 voltage regulation, the TPS53622 provides two synchronized rails from a single 12V bus. The D-CAP+ control loop responds to sudden compute load changes within microseconds, and USR technology reduces undershoot during the heaviest transients, protecting processor timing margins. Designers benefit from the PMBus interface for firmware-driven configuration and from NVM for storing per-board calibration data, which improves production consistency across large HPC clusters where hundreds of identical rails must behave identically.
推荐
Data Center 12V Bus Conversion
Data center racks distribute 12V on the middle bus, and the TPS53622 converts this bus efficiently to low-voltage CPU-side rails. Its compatibility with TI NexFET power stages integrates the MOSFETs, drivers, and current sensing into one device, achieving efficiency levels necessary to control rack power budgets and thermal loads. The controller's built-in NVM removes external configuration EEPROMs, cutting component count. PMBus reporting supports the data center infrastructure management layer, letting operators track per-rail current draw and flag degraded power stages before failures affect service availability.
推荐
Storage System Power Management
Enterprise storage controllers built on VR13-compatible processors use the TPS53622 for their core and I/O rails. The dual-channel 1+1 configuration lets a single controller power both the storage processor core and an auxiliary rail, simplifying sequencing. D-CAP+ stability with low-ESR ceramic output capacitors suits the dense, low-profile layouts of NVMe backplanes and JBOD controller boards. PMBus fault reporting lets storage system firmware log power events for predictive maintenance, while the -40C to +125C operating range supports harsh enclosure environments near drive bays.
推荐
VR13 Reference Design Reuse
TI provides reference designs pairing the TPS53622 with two CSD95490Q5MC power stages for 12V-to-1V conversion at 40A (20A per phase). Teams designing new VR13 server boards can reuse this validated layout, including power stage placement, current loop routing, and decoupling strategy, shortening design cycles significantly. The reference design demonstrates correct SVID integration and PMBus configuration through NVM. Because the controller handles loop compensation internally via D-CAP+, adaptation to different output voltages requires only NVM setting changes rather than re-tuning an external compensation network, reducing redesign risk.
推荐
推荐产品汇总
工程参考数据： TPS53622RSBT ——对比、设计指导和合规信息。
选型指南
与替代料对比
| 参数 | 本产品 | TPS53624 | TPS53632GRSMT | TPS536C9T | TPS53315 |
|---|---|---|---|---|---|
| Package | 40-WQFN (5x5 mm) | 40-WQFN | 40-WQFN | 40-WQFN | 40-WQFN |
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| VR Protocol | Intel VR13 SVID | VR13 SVID | VR13 family | Newer generation VR | Legacy D-CAP |
| PMBus Interface | Yes | Yes | Yes | Yes | No |
| Built-in NVM | Yes | Yes | Yes | Yes | No |
| Control Architecture | D-CAP+ with USR | D-CAP+ family | D-CAP+ family | Newer D-CAP generation | D-CAP |
关键差异点
- Integrated VR13 SVID logic （对比 TPS53315)
- D-CAP+ with undershoot reduction (USR) （对比 TPS53632GRSMT)
- Proven drop-in ecosystem with NexFET power stages （对比 TPS536C9T)
设计说明
Route the controller-to-power-stage traces (PWM, differential current sense) short and symmetrical between phases. Use TI's VR13 reference design layout with two CSD95490Q5MC stages for 12V-to-1V at 40A as the starting point. Connect the exposed thermal pad of the 40-pin WQFN to a solid ground plane with a via array to manage heat and minimize ground bounce between controller and power stages.
The TPS53622 relies on NVM defaults at power-up before SVID or PMBus configuration loads. Program the NVM during production to match the target rail voltages and sequencing, otherwise the controller boots with factory defaults that may not suit your platform. Verify PMBus pull-up levels and bus capacitance against the PMBus specification segment used.
D-CAP+ uses output voltage ripple for regulation, so place output capacitors close to the sense point and use low-ESR ceramics per the datasheet recommendation. Excessive trace inductance between the output capacitors and load distorts the ripple sensed by the controller and can degrade transient response and current sharing between channels.
合规信息
RoHS compliant per TI product listing. Server-grade controller; AEC-Q100 not applicable. Additional environmental data available on TI.com quality pages.
