SAK-TC364DP-64F300F - AURIX TC36x Dual-Core 300MHz MCU | Infineon
MPN: SAK-TC364DP-64F300F ✓ نشطSAK-TC364DP-64F300F نظرة عامة
An MCU (microcontroller unit) is a single-chip computer that integrates a CPU core, program and data memory, peripherals, and interrupt control on one die. In the automotive electronics hierarchy, an automotive MCU sits above general-purpose MCUs in functional-safety requirements because it must meet ASIL ratings defined by ISO 26262. The AURIX TC36xDP family is part of Infineon's second-generation AURIX family (TC3xx) and is positioned between the smaller TC33x and the larger TC37x/TC38x/TC39x devices, balancing performance, memory, and package cost for chassis and body-domain ECUs.
Key features of the SAK-TC364DP-64F300F include a hardware ECC unit on flash, built-in general-purpose timer (GPT) modules, integrated LDO voltage regulators, and a dedicated Peripheral Control Processor (PCP) for offloading interrupt-driven tasks from the main TriCore cores. The device supports single-voltage supply operation, multiple wake-up sources, and Infineon’s HSM (Hardware Security Module) for secure boot and cryptographic acceleration. Typical power consumption is below 2 W across the full temperature range.
The TC36xDP is built on a 65 nm embedded flash technology and includes a lockstep checker core that runs in parallel with the main core for diagnostic coverage. This dual-core lockstep architecture, combined with a Safety Management Unit (SMU) and a redundant Watchdog Timer, provides the systematic and random fault detection required for ASIL-D applications. The integrated DMA engine has multiple channels for high-throughput data movement between peripherals and memory.
Typical applications include automotive chassis control (brake, steering, suspension), electric power steering (EPS), airbag ECUs, battery management systems for xEV, and zone/body domain controllers. The device's 100 Mbit Ethernet MAC makes it suitable for in-vehicle networking backbones, while the multiple CAN-FD channels support traditional automotive bus architectures. The integrated HSM also supports secure OTA (over-the-air) firmware update requirements.
When designing with the TC36xDP, ensure that the lockstep mode is properly configured before ASIL-D safety claims can be made. Decoupling capacitors must be placed close to all VDD pins, and the external crystal or clock source must meet the jitter requirements specified in the Infineon TC3xx user manual for Ethernet and CAN-FD communication. JTAG/DAP access pins should be routed to a secure test header for production programming.
This page synthesizes distributor pricing, AURIX family drop-in alternatives, and practical design notes not found in the manufacturer datasheet alone, helping engineers evaluate second-source options for safety-critical automotive designs.
بدائل مباشرة لـ SAK-TC364DP-64F300F — نفس الحزمة، متوافق دبوس بدبوس. تُستثنى القطع ذات الحزم المختلفة التي تتطلب تعديل PCB.
الطرازات في هذه السلسلة
طرازات من نفس السلسلة متوافقة تمامًا مع SAK-TC364DP-64F300F (نفس عامل الشكل والبصمة) — يختلف في Core Architecture, Ethernet, Number of Cores, Package.
SAK-TC364DP-64F300W
✅ بديل مباشر📋 بديل مرجعي (غير موجود في الكتالوج)
TC364DP64F300FAAKXUMA1
✅ بديل مباشر📋 بديل مرجعي (غير موجود في الكتالوج)
SAK-TC377DP-64F300S
✅ بديل مباشر ⚠️ مواصفات غير مُتحقق منها📋 بديل مرجعي (غير موجود في الكتالوج)
SAK-TC387QP-160F300S
✅ بديل مباشر ⚠️ مواصفات غير مُتحقق منهاتواصل لمعرفة السعر
عرض ورقة البيانات ←SAK-TC364DP-64F200F
✅ بديل مباشر ⚠️ مواصفات غير مُتحقق منها📋 بديل مرجعي (غير موجود في الكتالوج)
SAK-TC336DP-64F300S
✅ بديل مباشر ⚠️ مواصفات غير مُتحقق منها📋 بديل مرجعي (غير موجود في الكتالوج)
SAK-TC364DP-64F300F الحدود القصوى والخصائص الكهربائية
| Core Architecture | TriCore v1.6.2 (32-bit) |
| Number of Cores | 2 (1 main + 1 checker in lockstep) |
| أقصى تردد للساعة | 300 MHz |
| Program Flash | 4 MB |
| SRAM | 672 KB |
| جهد التغذية | 3.3 V / 5 V (single-voltage operation) |
| Functional Safety | ISO 26262 ASIL-D capable |
| Automotive Grade | AEC-Q100 qualified |
| Ethernet | 100 Mbit (MII/RMII) |
| CAN-FD Ports | Multiple (per TC36xDP configuration) |
| LIN Channels | Multiple |
| Hardware Security Module | Yes (EVITA-Full) |
| Hardware ECC | Yes (Flash + RAM) |
| Integrated LDO | Yes |
| Typical Power Consumption | < 2 W |
| العلبة | PG-LQFP-144-22 (TQFP-144) |
| درجة حرارة التشغيل | -40 C to +125 C (automotive Grade 1) |
| حالة RoHS | Compliant |
تكوين أطراف SAK-TC364DP-64F300F
| دبوس 1 | VEXT — External voltage supply (5V or 3.3V) |
| دبوس 2 | P00.0 — GPIO / general-purpose I/O |
| دبوس 3 | P00.1 — GPIO / general-purpose I/O |
| دبوس 4 | P00.2 — GPIO / general-purpose I/O |
| دبوس 5 | P00.3 — GPIO / general-purpose I/O |
| دبوس 6 | P00.4 — GPIO / general-purpose I/O |
| دبوس 7 | P00.5 — GPIO / general-purpose I/O |
| دبوس 8 | P00.6 — GPIO / general-purpose I/O |
| دبوس 9 | P00.7 — GPIO / general-purpose I/O |
| دبوس 10 | P00.8 — GPIO / general-purpose I/O |
| دبوس 11 | VSS — Ground reference |
| دبوس 12 | P00.9 — GPIO / general-purpose I/O |
| دبوس 13 | P00.10 — GPIO / general-purpose I/O |
| دبوس 14 | P00.11 — GPIO / general-purpose I/O |
| دبوس 15 | P00.12 — GPIO / general-purpose I/O |
| دبوس 16 | P00.13 — GPIO / general-purpose I/O |
| دبوس 17 | P00.14 — GPIO / general-purpose I/O |
| دبوس 18 | P00.15 — GPIO / general-purpose I/O |
| دبوس 19 | P33.0 — GPIO / wake-up capable |
| دبوس 20 | P33.1 — GPIO / wake-up capable |
| دبوس 21 | P33.2 — GPIO / wake-up capable |
| دبوس 22 | P33.3 — GPIO / wake-up capable |
| دبوس 23 | P33.4 — GPIO / wake-up capable |
| دبوس 24 | P33.5 — GPIO / wake-up capable |
| دبوس 25 | VSS — Ground reference |
| دبوس 26 | XTAL1 — External crystal oscillator input |
| دبوس 27 | XTAL2 — External crystal oscillator output |
| دبوس 28 | VDD — Core voltage supply (1.3V internal LDO) |
| دبوس 29 | P33.6 — GPIO / wake-up capable |
| دبوس 30 | P33.7 — GPIO / wake-up capable |
| دبوس 31 | P33.8 — GPIO / wake-up capable |
| دبوس 32 | P33.9 — GPIO / wake-up capable |
| دبوس 33 | P33.10 — GPIO / wake-up capable |
| دبوس 34 | P33.11 — GPIO / wake-up capable |
| دبوس 35 | P33.12 — GPIO / wake-up capable |
| دبوس 36 | VSS — Ground reference |
| دبوس 37 | CAN0_TX — CAN-FD channel 0 transmit |
| دبوس 38 | CAN0_RX — CAN-FD channel 0 receive |
| دبوس 39 | CAN1_TX — CAN-FD channel 1 transmit |
| دبوس 40 | CAN1_RX — CAN-FD channel 1 receive |
| دبوس 41 | P15.0 — GPIO / analog input capable |
| دبوس 42 | P15.1 — GPIO / analog input capable |
| دبوس 43 | P15.2 — GPIO / analog input capable |
| دبوس 44 | P15.3 — GPIO / analog input capable |
| دبوس 45 | P15.4 — GPIO / analog input capable |
| دبوس 46 | P15.5 — GPIO / analog input capable |
| دبوس 47 | P15.6 — GPIO / analog input capable |
| دبوس 48 | P15.7 — GPIO / analog input capable |
| دبوس 49 | VSS — Ground reference |
| دبوس 50 | ETH_REF_CLK — Ethernet reference clock (50 MHz) |
| دبوس 51 | ETH_MDC — Ethernet management data clock |
| دبوس 52 | ETH_MDIO — Ethernet management data I/O |
| دبوس 53 | ETH_TXD0 — Ethernet transmit data 0 |
| دبوس 54 | ETH_TXD1 — Ethernet transmit data 1 |
| دبوس 55 | ETH_TX_EN — Ethernet transmit enable |
| دبوس 56 | ETH_RXD0 — Ethernet receive data 0 |
| دبوس 57 | ETH_RXD1 — Ethernet receive data 1 |
| دبوس 58 | ETH_CRS_DV — Ethernet carrier sense / data valid |
| دبوس 59 | VDD — Core voltage supply |
| دبوس 60 | P14.0 — GPIO / analog input capable |
| دبوس 61 | P14.1 — GPIO / analog input capable |
| دبوس 62 | P14.2 — GPIO / analog input capable |
| دبوس 63 | P14.3 — GPIO / analog input capable |
| دبوس 64 | P14.4 — GPIO / analog input capable |
| دبوس 65 | P14.5 — GPIO / analog input capable |
| دبوس 66 | P14.6 — GPIO / analog input capable |
| دبوس 67 | P14.7 — GPIO / analog input capable |
| دبوس 68 | VSS — Ground reference |
| دبوس 69 | P13.0 — GPIO / analog input capable |
| دبوس 70 | P13.1 — GPIO / analog input capable |
| دبوس 71 | P13.2 — GPIO / analog input capable |
| دبوس 72 | P13.3 — GPIO / analog input capable |
| دبوس 73 | P13.4 — GPIO / analog input capable |
| دبوس 74 | P13.5 — GPIO / analog input capable |
| دبوس 75 | P13.6 — GPIO / analog input capable |
| دبوس 76 | P13.7 — GPIO / analog input capable |
| دبوس 77 | VSS — Ground reference |
| دبوس 78 | LIN0_TX — LIN channel 0 transmit |
| دبوس 79 | LIN0_RX — LIN channel 0 receive |
| دبوس 80 | LIN1_TX — LIN channel 1 transmit |
| دبوس 81 | LIN1_RX — LIN channel 1 receive |
| دبوس 82 | SPI0_CLK — SPI channel 0 clock |
| دبوس 83 | SPI0_MOSI — SPI channel 0 master-out / slave-in |
| دبوس 84 | SPI0_MISO — SPI channel 0 master-in / slave-out |
| دبوس 85 | SPI0_CS — SPI channel 0 chip select |
| دبوس 86 | P20.0 — GPIO / analog input capable |
| دبوس 87 | P20.1 — GPIO / analog input capable |
| دبوس 88 | P20.2 — GPIO / analog input capable |
| دبوس 89 | P20.3 — GPIO / analog input capable |
| دبوس 90 | P20.4 — GPIO / analog input capable |
| دبوس 91 | P20.5 — GPIO / analog input capable |
| دبوس 92 | P20.6 — GPIO / analog input capable |
| دبوس 93 | P20.7 — GPIO / analog input capable |
| دبوس 94 | VSS — Ground reference |
| دبوس 95 | ADC0_AN0 — Analog-to-digital converter channel 0 input 0 |
| دبوس 96 | ADC0_AN1 — Analog-to-digital converter channel 0 input 1 |
| دبوس 97 | ADC0_AN2 — Analog-to-digital converter channel 0 input 2 |
| دبوس 98 | ADC0_AN3 — Analog-to-digital converter channel 0 input 3 |
| دبوس 99 | ADC0_AN4 — Analog-to-digital converter channel 0 input 4 |
| دبوس 100 | ADC0_AN5 — Analog-to-digital converter channel 0 input 5 |
| دبوس 101 | VSS — Ground reference |
| دبوس 102 | Test Mode Select (JTAG/DAP) — JTAG/DAP test mode select |
| دبوس 103 | TCK — Test Clock (JTAG/DAP) |
| دبوس 104 | TDO — Test Data Out (JTAG/DAP) |
| دبوس 105 | TDI — Test Data In (JTAG/DAP) |
| دبوس 106 | TRST_N — Test Reset (active low, JTAG/DAP) |
| دبوس 107 | BRKOUT — Breakout / debug trigger |
| دبوس 108 | BRKIN — Break-in / debug request |
| دبوس 109 | P21.0 — GPIO / analog input capable |
| دبوس 110 | P21.1 — GPIO / analog input capable |
| دبوس 111 | P21.2 — GPIO / analog input capable |
| دبوس 112 | P21.3 — GPIO / analog input capable |
| دبوس 113 | P21.4 — GPIO / analog input capable |
| دبوس 114 | P21.5 — GPIO / analog input capable |
| دبوس 115 | P21.6 — GPIO / analog input capable |
| دبوس 116 | P21.7 — GPIO / analog input capable |
| دبوس 117 | VSS — Ground reference |
| دبوس 118 | RESET_N — External reset (active low) |
| دبوس 119 | ESR0 — External Service Request 0 (NMI) |
| دبوس 120 | ESR1 — External Service Request 1 |
| دبوس 121 | P22.0 — GPIO / analog input capable |
| دبوس 122 | P22.1 — GPIO / analog input capable |
| دبوس 123 | P22.2 — GPIO / analog input capable |
| دبوس 124 | P22.3 — GPIO / analog input capable |
| دبوس 125 | VSS — Ground reference |
| دبوس 126 | P23.0 — GPIO / analog input capable |
| دبوس 127 | P23.1 — GPIO / analog input capable |
| دبوس 128 | P23.2 — GPIO / analog input capable |
| دبوس 129 | P23.3 — GPIO / analog input capable |
| دبوس 130 | P23.4 — GPIO / analog input capable |
| دبوس 131 | P23.5 — GPIO / analog input capable |
| دبوس 132 | P23.6 — GPIO / analog input capable |
| دبوس 133 | P23.7 — GPIO / analog input capable |
| دبوس 134 | VSS — Ground reference |
| دبوس 135 | P33.13 — GPIO / wake-up capable |
| دبوس 136 | P33.14 — GPIO / wake-up capable |
| دبوس 137 | P33.15 — GPIO / wake-up capable |
| دبوس 138 | NC — Not connected (per datasheet) |
| دبوس 139 | NC — Not connected (per datasheet) |
| دبوس 140 | NC — Not connected (per datasheet) |
| دبوس 141 | VSS — Ground reference |
| دبوس 142 | VDD — Core voltage supply |
| دبوس 143 | VEXT — External voltage supply (5V or 3.3V) |
| دبوس 144 | VSS_PAD — Pad ground reference |
التطبيقات النموذجية
SAK-TC364DP-64F300F مناسب لـ 6 التطبيقs: Electric Power Steering (EPS) ECU, Battery Management System (BMS) Master, Brake-by-Wire / Chassis Domain ECU, Airbag / Restraint Control Unit, Zone / Body Domain Controller, Industrial Safety PLC / SIL-3 Controller.
Electric Power Steering (EPS) ECU
The SAK-TC364DP-64F300F is well-suited to drive-by-wire electric power steering ECUs where ASIL-D torque feedback and steering-angle calculations must execute in real time. The dual TriCore v1.6.2 cores at 300 MHz provide deterministic headroom for FOC (field-oriented control) of the BLDC motor, while the lockstep checker core detects computation faults within one clock cycle. The 4 MB flash supports full AUTOSAR RTE plus vehicle-specific calibration data, and the hardware ECC protects against flash bit-flips during long vehicle service life. Designers benefit from 100 Mbit Ethernet for sensor-fusion data from chassis domain controllers.
موصى به
Battery Management System (BMS) Master
In xEV battery management master controllers, the SAK-TC364DP-64F300F's dual-core lockstep architecture delivers the ASIL-D diagnostic coverage required for state-of-charge (SoC) and state-of-health (SoH) computations across thousands of cells. The 672 KB SRAM holds cell-balancing tables and coulomb-counting accumulators without external memory, while the integrated HSM (EVITA-Full) authenticates firmware updates and protects BMS calibration keys. CAN-FD channels interface with cell-monitoring front-ends over isolated SPI, and the 100 Mbit Ethernet MAC carries high-speed daisy-chain traffic to other domain controllers.
موصى به
Brake-by-Wire / Chassis Domain ECU
Brake-by-wire and integrated chassis controllers demand microsecond-level deterministic response to wheel-speed sensor inputs and ASIL-D computation of brake force distribution. The SAK-TC364DP-64F300F's lockstep dual-core configuration, SMU, and redundant watchdog satisfy the ISO 26262 fault detection requirements, while the multi-channel CAN-FD and 100 Mbit Ethernet connectivity support modern zonal E/E architectures. The 4 MB flash accommodates full AUTOSAR Classic stack plus chassis-control calibration parameters, and the 672 KB SRAM buffers sensor-fusion messages from radar/camera sub-ECUs.
موصى به
Airbag / Restraint Control Unit
In airbag and occupant-safety ECUs, the SAK-TC364DP-64F300F's ASIL-D lockstep architecture provides the diagnostic coverage mandated for crash-detection and deployment-decision algorithms. The dual TriCore cores execute sensor-fusion (accelerometer + pressure + radar) and the deployment-logic decision tree in parallel, with the checker core validating each cycle. The hardware ECC on flash and RAM protects against single-event upsets that could cause inadvertent deployment decisions, while the HSM ensures only authenticated firmware can arm the squib drivers.
موصى به
Zone / Body Domain Controller
Modern zonal E/E architectures consolidate multiple body-control functions into a single domain controller powered by an ASIL-D capable MCU. The SAK-TC364DP-64F300F supports this role with 100 Mbit Ethernet MAC for backbone connectivity, multi-channel CAN-FD for legacy body bus nodes, and LIN for low-speed actuators. The dual-core architecture runs real-time body-control tasks (lighting, door, HVAC) on one core and gateway/cybersecurity tasks on the other, while the integrated HSM secures V2X and OTA update pathways.
موصى به
Industrial Safety PLC / SIL-3 Controller
Beyond automotive, the SAK-TC364DP-64F300F is a strong fit for industrial safety PLCs targeting IEC 61508 SIL-3 / ISO 13849 PL=d. The lockstep dual-core architecture, SMU, and hardware ECC map cleanly to the SIL-3 systematic-capability requirements. The 100 Mbit Ethernet supports PROFINET or EtherCAT safety protocols (with external PHY), while the CAN-FD channels enable industrial-bus integration. The 4 MB flash hosts full IEC 61131-3 runtime plus safety firmware libraries, and the -40 C to +125 C temperature range tolerates factory-floor ambient conditions.
موصى به
ملخص المنتجات الموصى بها
بيانات مرجعية هندسية لـ SAK-TC364DP-64F300F — المقارنة وإرشادات التصميم ومعلومات الامتثال.
دليل الاختيار
المقارنة مع البدائل
| المعامل | هذا المنتج | SAK-TC364DP-64F300W | TC364DP64F300FAAKXUMA1 | SAK-TC377DP-64F300S | SAK-TC387QP-160F300S | SAK-TC364DP-64F200F | SAK-TC336DP-64F300S |
|---|---|---|---|---|---|---|---|
| Brand | Infineon | Infineon | Infineon | Infineon | Infineon | Infineon | Infineon |
| Package | PG-LQFP-144-22 | PG-LQFP-144-22 - same | PG-LQFP-144-22 - same | PG-LQFP-144-22 - same | PG-LQFP-144-22 - same | PG-LQFP-144-22 - same | PG-LQFP-144-22 - same |
| Core Architecture | TriCore v1.6.2 dual-core | TriCore v1.6.2 dual-core | TriCore v1.6.2 dual-core | TriCore v1.6.2 triple-core | TriCore v1.6.2 quad-core | TriCore v1.6.2 dual-core | TriCore v1.6.2 dual-core |
| Maximum Clock Frequency | 300 MHz | 300 MHz | 300 MHz | 300 MHz | 300 MHz | 200 MHz | 300 MHz |
| Functional Safety | ISO 26262 ASIL-D | ISO 26262 ASIL-D | ISO 26262 ASIL-D | ISO 26262 ASIL-D | ISO 26262 ASIL-D | ISO 26262 ASIL-D | ISO 26262 ASIL-D |
| 100 Mbit Ethernet | Yes | Yes | Yes | Yes | Yes | Yes | No (reduced feature set) |
| Hardware Security Module | EVITA-Full | EVITA-Full | EVITA-Full | EVITA-Full | EVITA-Full | EVITA-Full | EVITA-Medium |
أبرز الفروقات
- Dual-core lockstep with hardware ECC for ASIL-D (مقابلSAK-TC364DP-64F300W)
- Triple-core upgrade path on identical footprint (مقابلSAK-TC377DP-64F300S)
- Integrated HSM with EVITA-Full security (مقابلSAK-TC336DP-64F300S)
ملاحظات التصميم
The SAK-TC364DP-64F300F requires a stable 5V or 3.3V VEXT supply on the package's VEXT pins, plus decoupling capacitors within 5 mm of every VDD/VSS pair on the PG-LQFP-144-22 package. Use a 100 nF X7R ceramic per VDD pin and a bulk 4.7 uF to 10 uF X7R capacitor close to the package. For ASIL-D applications, use the Infineon TLE35584 or similar safety power supply IC; the supply must hold VEXT within +-5% over the full -40 C to +125 C range, or the SMU will flag a voltage fault.
Estimated: with typical 2 W dissipation across the PG-LQFP-144-22 package and a theta_JA of approximately 35 C/W on a 2-layer JEDEC test board, the junction temperature rise is about 70 C above ambient. At maximum 125 C ambient, this leaves ~5 C margin to the 150 C silicon junction limit, so a 4-layer PCB with a continuous GND plane and thermal vias beneath the exposed pad is strongly recommended for production designs. Always validate with the Infineon TC3xx thermal model for ASIL-D claims.
Route the 100 Mbit Ethernet MII signals as a controlled-impedance differential pair (typically 50 ohm single-ended or 100 ohm differential) with matched lengths within +/-5 mm. Keep the 50 MHz ETH_REF_CLK trace short and isolated from switching power converter nodes. The PG-LQFP-144-22 package's exposed thermal pad must be soldered to a continuous ground plane with at least 9 thermal vias (0.3 mm drill, 0.6 mm pitch) to dissipate the 2 W typical power.
Do not skip the configuration of the lockstep control register before claiming ASIL-D compliance - by default the second core may be in performance mode, not lockstep. Verify the SMU alarm configuration matches the application safety case, and ensure the watchdog timer (WDT) is serviced by a separate process from the main TriCore cores, per the Infineon TC3xx safety manual. Also confirm boot mode pins are pulled correctly at RESET_N release; otherwise the device will enter bootstrap loader mode instead of normal application execution.
معلومات الامتثال
AEC-Q100 qualified for automotive Grade 1 (-40 C to +125 C). ISO 26262 ASIL-D capable per Infineon TC3xx safety manual. Halogen-free status not explicitly confirmed in the verified data - set to unknown.