SAK-TC364DP-64F300F - AURIX TC36x Dual-Core 300MHz MCU | Infineon
Référence : SAK-TC364DP-64F300F ✓ Actif| Qté | Prix unitaire | Total |
|---|---|---|
| 1 | $24.5 | $24,50 |
| 10 | $22.1 | $221,00 |
| 100 | $19.8 | $1 980,00 |
| 500 | $17.45 | $8 725,00 |
| 1 000 | $15.2 | $15 200,00 |
SAK-TC364DP-64F300F Présentation
An MCU (microcontroller unit) is a single-chip computer that integrates a CPU core, program and data memory, peripherals, and interrupt control on one die. In the automotive electronics hierarchy, an automotive MCU sits above general-purpose MCUs in functional-safety requirements because it must meet ASIL ratings defined by ISO 26262. The AURIX TC36xDP family is part of Infineon's second-generation AURIX family (TC3xx) and is positioned between the smaller TC33x and the larger TC37x/TC38x/TC39x devices, balancing performance, memory, and package cost for chassis and body-domain ECUs.
Key features of the SAK-TC364DP-64F300F include a hardware ECC unit on flash, built-in general-purpose timer (GPT) modules, integrated LDO voltage regulators, and a dedicated Peripheral Control Processor (PCP) for offloading interrupt-driven tasks from the main TriCore cores. The device supports single-voltage supply operation, multiple wake-up sources, and Infineon’s HSM (Hardware Security Module) for secure boot and cryptographic acceleration. Typical power consumption is below 2 W across the full temperature range.
The TC36xDP is built on a 65 nm embedded flash technology and includes a lockstep checker core that runs in parallel with the main core for diagnostic coverage. This dual-core lockstep architecture, combined with a Safety Management Unit (SMU) and a redundant Watchdog Timer, provides the systematic and random fault detection required for ASIL-D applications. The integrated DMA engine has multiple channels for high-throughput data movement between peripherals and memory.
Typical applications include automotive chassis control (brake, steering, suspension), electric power steering (EPS), airbag ECUs, battery management systems for xEV, and zone/body domain controllers. The device's 100 Mbit Ethernet MAC makes it suitable for in-vehicle networking backbones, while the multiple CAN-FD channels support traditional automotive bus architectures. The integrated HSM also supports secure OTA (over-the-air) firmware update requirements.
When designing with the TC36xDP, ensure that the lockstep mode is properly configured before ASIL-D safety claims can be made. Decoupling capacitors must be placed close to all VDD pins, and the external crystal or clock source must meet the jitter requirements specified in the Infineon TC3xx user manual for Ethernet and CAN-FD communication. JTAG/DAP access pins should be routed to a secure test header for production programming.
This page synthesizes distributor pricing, AURIX family drop-in alternatives, and practical design notes not found in the manufacturer datasheet alone, helping engineers evaluate second-source options for safety-critical automotive designs.
Alternatives de remplacement direct pour SAK-TC364DP-64F300F — même boîtier, compatible broche à broche. Les références à boîtier différent nécessitant une retouche du PCB sont exclues.
Variantes de cette série
Modèles de la même série directement compatibles avec SAK-TC364DP-64F300F (même facteur de forme et même empreinte) — différant par Core Architecture, Ethernet, Number of Cores, Package.
Outil de comparaison rapide — sélectionnez des références alternatives pour une comparaison côte à côte :
SAK-TC364DP-64F300W
✅ Remplacement direct📋 Alternative de référence (hors catalogue)
TC364DP64F300FAAKXUMA1
✅ Remplacement direct📋 Alternative de référence (hors catalogue)
SAK-TC377DP-64F300S
✅ Remplacement direct ⚠️ Spécifications non vérifiées📋 Alternative de référence (hors catalogue)
SAK-TC387QP-160F300S
✅ Remplacement direct ⚠️ Spécifications non vérifiées✓ En stock
$25.95 / unité
Voir la fiche technique →SAK-TC364DP-64F200F
✅ Remplacement direct ⚠️ Spécifications non vérifiées📋 Alternative de référence (hors catalogue)
SAK-TC336DP-64F300S
✅ Remplacement direct ⚠️ Spécifications non vérifiées📋 Alternative de référence (hors catalogue)
SAK-TC364DP-64F300F Valeurs maximales et caractéristiques électriques
| Core Architecture | TriCore v1.6.2 (32-bit) |
| Number of Cores | 2 (1 main + 1 checker in lockstep) |
| Fréquence d'horloge maximale | 300 MHz |
| Program Flash | 4 MB |
| SRAM | 672 KB |
| Tension d'alimentation | 3.3 V / 5 V (single-voltage operation) |
| Functional Safety | ISO 26262 ASIL-D capable |
| Automotive Grade | AEC-Q100 qualified |
| Ethernet | 100 Mbit (MII/RMII) |
| CAN-FD Ports | Multiple (per TC36xDP configuration) |
| LIN Channels | Multiple |
| Hardware Security Module | Yes (EVITA-Full) |
| Hardware ECC | Yes (Flash + RAM) |
| Integrated LDO | Yes |
| Typical Power Consumption | < 2 W |
| Boîtier | PG-LQFP-144-22 (TQFP-144) |
| Température de fonctionnement | -40 C to +125 C (automotive Grade 1) |
| Statut RoHS | Compliant |
Configuration des broches de SAK-TC364DP-64F300F
| Broche 1 | VEXT — External voltage supply (5V or 3.3V) |
| Broche 2 | P00.0 — GPIO / general-purpose I/O |
| Broche 3 | P00.1 — GPIO / general-purpose I/O |
| Broche 4 | P00.2 — GPIO / general-purpose I/O |
| Broche 5 | P00.3 — GPIO / general-purpose I/O |
| Broche 6 | P00.4 — GPIO / general-purpose I/O |
| Broche 7 | P00.5 — GPIO / general-purpose I/O |
| Broche 8 | P00.6 — GPIO / general-purpose I/O |
| Broche 9 | P00.7 — GPIO / general-purpose I/O |
| Broche 10 | P00.8 — GPIO / general-purpose I/O |
| Broche 11 | VSS — Ground reference |
| Broche 12 | P00.9 — GPIO / general-purpose I/O |
| Broche 13 | P00.10 — GPIO / general-purpose I/O |
| Broche 14 | P00.11 — GPIO / general-purpose I/O |
| Broche 15 | P00.12 — GPIO / general-purpose I/O |
| Broche 16 | P00.13 — GPIO / general-purpose I/O |
| Broche 17 | P00.14 — GPIO / general-purpose I/O |
| Broche 18 | P00.15 — GPIO / general-purpose I/O |
| Broche 19 | P33.0 — GPIO / wake-up capable |
| Broche 20 | P33.1 — GPIO / wake-up capable |
| Broche 21 | P33.2 — GPIO / wake-up capable |
| Broche 22 | P33.3 — GPIO / wake-up capable |
| Broche 23 | P33.4 — GPIO / wake-up capable |
| Broche 24 | P33.5 — GPIO / wake-up capable |
| Broche 25 | VSS — Ground reference |
| Broche 26 | XTAL1 — External crystal oscillator input |
| Broche 27 | XTAL2 — External crystal oscillator output |
| Broche 28 | VDD — Core voltage supply (1.3V internal LDO) |
| Broche 29 | P33.6 — GPIO / wake-up capable |
| Broche 30 | P33.7 — GPIO / wake-up capable |
| Broche 31 | P33.8 — GPIO / wake-up capable |
| Broche 32 | P33.9 — GPIO / wake-up capable |
| Broche 33 | P33.10 — GPIO / wake-up capable |
| Broche 34 | P33.11 — GPIO / wake-up capable |
| Broche 35 | P33.12 — GPIO / wake-up capable |
| Broche 36 | VSS — Ground reference |
| Broche 37 | CAN0_TX — CAN-FD channel 0 transmit |
| Broche 38 | CAN0_RX — CAN-FD channel 0 receive |
| Broche 39 | CAN1_TX — CAN-FD channel 1 transmit |
| Broche 40 | CAN1_RX — CAN-FD channel 1 receive |
| Broche 41 | P15.0 — GPIO / analog input capable |
| Broche 42 | P15.1 — GPIO / analog input capable |
| Broche 43 | P15.2 — GPIO / analog input capable |
| Broche 44 | P15.3 — GPIO / analog input capable |
| Broche 45 | P15.4 — GPIO / analog input capable |
| Broche 46 | P15.5 — GPIO / analog input capable |
| Broche 47 | P15.6 — GPIO / analog input capable |
| Broche 48 | P15.7 — GPIO / analog input capable |
| Broche 49 | VSS — Ground reference |
| Broche 50 | ETH_REF_CLK — Ethernet reference clock (50 MHz) |
| Broche 51 | ETH_MDC — Ethernet management data clock |
| Broche 52 | ETH_MDIO — Ethernet management data I/O |
| Broche 53 | ETH_TXD0 — Ethernet transmit data 0 |
| Broche 54 | ETH_TXD1 — Ethernet transmit data 1 |
| Broche 55 | ETH_TX_EN — Ethernet transmit enable |
| Broche 56 | ETH_RXD0 — Ethernet receive data 0 |
| Broche 57 | ETH_RXD1 — Ethernet receive data 1 |
| Broche 58 | ETH_CRS_DV — Ethernet carrier sense / data valid |
| Broche 59 | VDD — Core voltage supply |
| Broche 60 | P14.0 — GPIO / analog input capable |
| Broche 61 | P14.1 — GPIO / analog input capable |
| Broche 62 | P14.2 — GPIO / analog input capable |
| Broche 63 | P14.3 — GPIO / analog input capable |
| Broche 64 | P14.4 — GPIO / analog input capable |
| Broche 65 | P14.5 — GPIO / analog input capable |
| Broche 66 | P14.6 — GPIO / analog input capable |
| Broche 67 | P14.7 — GPIO / analog input capable |
| Broche 68 | VSS — Ground reference |
| Broche 69 | P13.0 — GPIO / analog input capable |
| Broche 70 | P13.1 — GPIO / analog input capable |
| Broche 71 | P13.2 — GPIO / analog input capable |
| Broche 72 | P13.3 — GPIO / analog input capable |
| Broche 73 | P13.4 — GPIO / analog input capable |
| Broche 74 | P13.5 — GPIO / analog input capable |
| Broche 75 | P13.6 — GPIO / analog input capable |
| Broche 76 | P13.7 — GPIO / analog input capable |
| Broche 77 | VSS — Ground reference |
| Broche 78 | LIN0_TX — LIN channel 0 transmit |
| Broche 79 | LIN0_RX — LIN channel 0 receive |
| Broche 80 | LIN1_TX — LIN channel 1 transmit |
| Broche 81 | LIN1_RX — LIN channel 1 receive |
| Broche 82 | SPI0_CLK — SPI channel 0 clock |
| Broche 83 | SPI0_MOSI — SPI channel 0 master-out / slave-in |
| Broche 84 | SPI0_MISO — SPI channel 0 master-in / slave-out |
| Broche 85 | SPI0_CS — SPI channel 0 chip select |
| Broche 86 | P20.0 — GPIO / analog input capable |
| Broche 87 | P20.1 — GPIO / analog input capable |
| Broche 88 | P20.2 — GPIO / analog input capable |
| Broche 89 | P20.3 — GPIO / analog input capable |
| Broche 90 | P20.4 — GPIO / analog input capable |
| Broche 91 | P20.5 — GPIO / analog input capable |
| Broche 92 | P20.6 — GPIO / analog input capable |
| Broche 93 | P20.7 — GPIO / analog input capable |
| Broche 94 | VSS — Ground reference |
| Broche 95 | ADC0_AN0 — Analog-to-digital converter channel 0 input 0 |
| Broche 96 | ADC0_AN1 — Analog-to-digital converter channel 0 input 1 |
| Broche 97 | ADC0_AN2 — Analog-to-digital converter channel 0 input 2 |
| Broche 98 | ADC0_AN3 — Analog-to-digital converter channel 0 input 3 |
| Broche 99 | ADC0_AN4 — Analog-to-digital converter channel 0 input 4 |
| Broche 100 | ADC0_AN5 — Analog-to-digital converter channel 0 input 5 |
| Broche 101 | VSS — Ground reference |
| Broche 102 | Test Mode Select (JTAG/DAP) — JTAG/DAP test mode select |
| Broche 103 | TCK — Test Clock (JTAG/DAP) |
| Broche 104 | TDO — Test Data Out (JTAG/DAP) |
| Broche 105 | TDI — Test Data In (JTAG/DAP) |
| Broche 106 | TRST_N — Test Reset (active low, JTAG/DAP) |
| Broche 107 | BRKOUT — Breakout / debug trigger |
| Broche 108 | BRKIN — Break-in / debug request |
| Broche 109 | P21.0 — GPIO / analog input capable |
| Broche 110 | P21.1 — GPIO / analog input capable |
| Broche 111 | P21.2 — GPIO / analog input capable |
| Broche 112 | P21.3 — GPIO / analog input capable |
| Broche 113 | P21.4 — GPIO / analog input capable |
| Broche 114 | P21.5 — GPIO / analog input capable |
| Broche 115 | P21.6 — GPIO / analog input capable |
| Broche 116 | P21.7 — GPIO / analog input capable |
| Broche 117 | VSS — Ground reference |
| Broche 118 | RESET_N — External reset (active low) |
| Broche 119 | ESR0 — External Service Request 0 (NMI) |
| Broche 120 | ESR1 — External Service Request 1 |
| Broche 121 | P22.0 — GPIO / analog input capable |
| Broche 122 | P22.1 — GPIO / analog input capable |
| Broche 123 | P22.2 — GPIO / analog input capable |
| Broche 124 | P22.3 — GPIO / analog input capable |
| Broche 125 | VSS — Ground reference |
| Broche 126 | P23.0 — GPIO / analog input capable |
| Broche 127 | P23.1 — GPIO / analog input capable |
| Broche 128 | P23.2 — GPIO / analog input capable |
| Broche 129 | P23.3 — GPIO / analog input capable |
| Broche 130 | P23.4 — GPIO / analog input capable |
| Broche 131 | P23.5 — GPIO / analog input capable |
| Broche 132 | P23.6 — GPIO / analog input capable |
| Broche 133 | P23.7 — GPIO / analog input capable |
| Broche 134 | VSS — Ground reference |
| Broche 135 | P33.13 — GPIO / wake-up capable |
| Broche 136 | P33.14 — GPIO / wake-up capable |
| Broche 137 | P33.15 — GPIO / wake-up capable |
| Broche 138 | NC — Not connected (per datasheet) |
| Broche 139 | NC — Not connected (per datasheet) |
| Broche 140 | NC — Not connected (per datasheet) |
| Broche 141 | VSS — Ground reference |
| Broche 142 | VDD — Core voltage supply |
| Broche 143 | VEXT — External voltage supply (5V or 3.3V) |
| Broche 144 | VSS_PAD — Pad ground reference |
Applications typiques
SAK-TC364DP-64F300F convient pour 6 applications: Electric Power Steering (EPS) ECU, Battery Management System (BMS) Master, Brake-by-Wire / Chassis Domain ECU, Airbag / Restraint Control Unit, Zone / Body Domain Controller, Industrial Safety PLC / SIL-3 Controller.
Electric Power Steering (EPS) ECU
The SAK-TC364DP-64F300F is well-suited to drive-by-wire electric power steering ECUs where ASIL-D torque feedback and steering-angle calculations must execute in real time. The dual TriCore v1.6.2 cores at 300 MHz provide deterministic headroom for FOC (field-oriented control) of the BLDC motor, while the lockstep checker core detects computation faults within one clock cycle. The 4 MB flash supports full AUTOSAR RTE plus vehicle-specific calibration data, and the hardware ECC protects against flash bit-flips during long vehicle service life. Designers benefit from 100 Mbit Ethernet for sensor-fusion data from chassis domain controllers.
Recommandé
Battery Management System (BMS) Master
In xEV battery management master controllers, the SAK-TC364DP-64F300F's dual-core lockstep architecture delivers the ASIL-D diagnostic coverage required for state-of-charge (SoC) and state-of-health (SoH) computations across thousands of cells. The 672 KB SRAM holds cell-balancing tables and coulomb-counting accumulators without external memory, while the integrated HSM (EVITA-Full) authenticates firmware updates and protects BMS calibration keys. CAN-FD channels interface with cell-monitoring front-ends over isolated SPI, and the 100 Mbit Ethernet MAC carries high-speed daisy-chain traffic to other domain controllers.
Recommandé
Brake-by-Wire / Chassis Domain ECU
Brake-by-wire and integrated chassis controllers demand microsecond-level deterministic response to wheel-speed sensor inputs and ASIL-D computation of brake force distribution. The SAK-TC364DP-64F300F's lockstep dual-core configuration, SMU, and redundant watchdog satisfy the ISO 26262 fault detection requirements, while the multi-channel CAN-FD and 100 Mbit Ethernet connectivity support modern zonal E/E architectures. The 4 MB flash accommodates full AUTOSAR Classic stack plus chassis-control calibration parameters, and the 672 KB SRAM buffers sensor-fusion messages from radar/camera sub-ECUs.
Recommandé
Airbag / Restraint Control Unit
In airbag and occupant-safety ECUs, the SAK-TC364DP-64F300F's ASIL-D lockstep architecture provides the diagnostic coverage mandated for crash-detection and deployment-decision algorithms. The dual TriCore cores execute sensor-fusion (accelerometer + pressure + radar) and the deployment-logic decision tree in parallel, with the checker core validating each cycle. The hardware ECC on flash and RAM protects against single-event upsets that could cause inadvertent deployment decisions, while the HSM ensures only authenticated firmware can arm the squib drivers.
Recommandé
Zone / Body Domain Controller
Modern zonal E/E architectures consolidate multiple body-control functions into a single domain controller powered by an ASIL-D capable MCU. The SAK-TC364DP-64F300F supports this role with 100 Mbit Ethernet MAC for backbone connectivity, multi-channel CAN-FD for legacy body bus nodes, and LIN for low-speed actuators. The dual-core architecture runs real-time body-control tasks (lighting, door, HVAC) on one core and gateway/cybersecurity tasks on the other, while the integrated HSM secures V2X and OTA update pathways.
Recommandé
Industrial Safety PLC / SIL-3 Controller
Beyond automotive, the SAK-TC364DP-64F300F is a strong fit for industrial safety PLCs targeting IEC 61508 SIL-3 / ISO 13849 PL=d. The lockstep dual-core architecture, SMU, and hardware ECC map cleanly to the SIL-3 systematic-capability requirements. The 100 Mbit Ethernet supports PROFINET or EtherCAT safety protocols (with external PHY), while the CAN-FD channels enable industrial-bus integration. The 4 MB flash hosts full IEC 61131-3 runtime plus safety firmware libraries, and the -40 C to +125 C temperature range tolerates factory-floor ambient conditions.
Recommandé
Récapitulatif des produits recommandés
Données de référence d'ingénierie pour SAK-TC364DP-64F300F — comparaison, recommandations de conception et informations de conformité.
Guide de sélection
Comparaison avec les alternatives
| Paramètre | Ce produit | SAK-TC364DP-64F300W | TC364DP64F300FAAKXUMA1 | SAK-TC377DP-64F300S | SAK-TC387QP-160F300S | SAK-TC364DP-64F200F | SAK-TC336DP-64F300S |
|---|---|---|---|---|---|---|---|
| Brand | Infineon | Infineon | Infineon | Infineon | Infineon | Infineon | Infineon |
| Package | PG-LQFP-144-22 | PG-LQFP-144-22 - same | PG-LQFP-144-22 - same | PG-LQFP-144-22 - same | PG-LQFP-144-22 - same | PG-LQFP-144-22 - same | PG-LQFP-144-22 - same |
| Core Architecture | TriCore v1.6.2 dual-core | TriCore v1.6.2 dual-core | TriCore v1.6.2 dual-core | TriCore v1.6.2 triple-core | TriCore v1.6.2 quad-core | TriCore v1.6.2 dual-core | TriCore v1.6.2 dual-core |
| Maximum Clock Frequency | 300 MHz | 300 MHz | 300 MHz | 300 MHz | 300 MHz | 200 MHz | 300 MHz |
| Functional Safety | ISO 26262 ASIL-D | ISO 26262 ASIL-D | ISO 26262 ASIL-D | ISO 26262 ASIL-D | ISO 26262 ASIL-D | ISO 26262 ASIL-D | ISO 26262 ASIL-D |
| 100 Mbit Ethernet | Yes | Yes | Yes | Yes | Yes | Yes | No (reduced feature set) |
| Hardware Security Module | EVITA-Full | EVITA-Full | EVITA-Full | EVITA-Full | EVITA-Full | EVITA-Full | EVITA-Medium |
Principaux différenciateurs
- Dual-core lockstep with hardware ECC for ASIL-D (vs SAK-TC364DP-64F300W)
- Triple-core upgrade path on identical footprint (vs SAK-TC377DP-64F300S)
- Integrated HSM with EVITA-Full security (vs SAK-TC336DP-64F300S)
Notes de conception
The SAK-TC364DP-64F300F requires a stable 5V or 3.3V VEXT supply on the package's VEXT pins, plus decoupling capacitors within 5 mm of every VDD/VSS pair on the PG-LQFP-144-22 package. Use a 100 nF X7R ceramic per VDD pin and a bulk 4.7 uF to 10 uF X7R capacitor close to the package. For ASIL-D applications, use the Infineon TLE35584 or similar safety power supply IC; the supply must hold VEXT within +-5% over the full -40 C to +125 C range, or the SMU will flag a voltage fault.
Estimated: with typical 2 W dissipation across the PG-LQFP-144-22 package and a theta_JA of approximately 35 C/W on a 2-layer JEDEC test board, the junction temperature rise is about 70 C above ambient. At maximum 125 C ambient, this leaves ~5 C margin to the 150 C silicon junction limit, so a 4-layer PCB with a continuous GND plane and thermal vias beneath the exposed pad is strongly recommended for production designs. Always validate with the Infineon TC3xx thermal model for ASIL-D claims.
Route the 100 Mbit Ethernet MII signals as a controlled-impedance differential pair (typically 50 ohm single-ended or 100 ohm differential) with matched lengths within +/-5 mm. Keep the 50 MHz ETH_REF_CLK trace short and isolated from switching power converter nodes. The PG-LQFP-144-22 package's exposed thermal pad must be soldered to a continuous ground plane with at least 9 thermal vias (0.3 mm drill, 0.6 mm pitch) to dissipate the 2 W typical power.
Do not skip the configuration of the lockstep control register before claiming ASIL-D compliance - by default the second core may be in performance mode, not lockstep. Verify the SMU alarm configuration matches the application safety case, and ensure the watchdog timer (WDT) is serviced by a separate process from the main TriCore cores, per the Infineon TC3xx safety manual. Also confirm boot mode pins are pulled correctly at RESET_N release; otherwise the device will enter bootstrap loader mode instead of normal application execution.
Informations de conformité
AEC-Q100 qualified for automotive Grade 1 (-40 C to +125 C). ISO 26262 ASIL-D capable per Infineon TC3xx safety manual. Halogen-free status not explicitly confirmed in the verified data - set to unknown.
