EP1810LC-30 vs EP1810LC-25 Comparison

Detailed side-by-side comparison of EP1810LC-30 by Altera and EP1810LC-25 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EP1810LC-30 EP1810LC-25
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $9.95 $8.40
Product Type Classic EPLD (Erasable Programmable Logic Device) —
Family Altera Classic EPLD —
Macrocells 48 48
Flip-Flops 48 (one per macrocell) —
Speed Grade (tPD) 30 ns —
Supply Voltage 5 V (typical) —
Technology CMOS, low-power (LC) CMOS EPLD (erasable programmable logic device)
Package JLCC-68 (68-pin J-Lead ceramic chip carrier) 68-pin JLCC (J-leaded ceramic chip carrier)
Programming Device programmer or JTAG —
Operating Temperature [DATA_NEEDED: temperature grade] [DATA_NEEDED: temperature grade for LC package]
Standby Current [DATA_NEEDED: ICC standby] —
Number of Pins 68 —
Number of I/O Pins [DATA_NEEDED: I/O count] —
Logic Blocks 48 macrocells —
RoHS Status unknown (legacy ceramic package) [DATA_NEEDED: RoHS compliance not confirmed in legacy datasheet]
Product Family — Altera Classic EPLD
Part Number — EP1810LC-25
Propagation Delay (tPD) — 25 ns
Dedicated Inputs — 12
I/O Pins — 48
External Clock Inputs — 4
Supply Voltage (VCC) — 5 V (TTL-compatible)
Operating Mode — Turbo-only (no slow-power mode)
Package Code — LC = 68-pin JLCC
Mounting Type — Surface Mount
Programmable Interconnect — Global + Local buses
Programming Method — Altera Classic programmer + MAX+PLUS II legacy flow
Lifecycle Status — Obsolete (legacy Altera Classic family)

Datasheets & Resources

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