EP20K400FC672-3 vs EP20K400FC672-3X Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP20K400FC672-3 sa pamamagitan ng Altera at EP20K400FC672-3X sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Altera
EP20K400FC672-3X EP20K400FC672-3X - APEX 20K 400K Gates FPGA, 672-BGA | Altera

EP20K400FC672-3X - APEX 20K 400K Gates FPGA, 672-BGA | Altera

EP20K400FC672-3X ⚠ Huling Pagbili

Pagsanggunian na paghahambing

Parametro EP20K400FC672-3 EP20K400FC672-3X
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Huling Pagbili
Family APEX 20K —
Device Logic Elements 16,640 cells —
Typical Gate Count 400,000 system gates —
Maximum User I/Os 502 —
Propagation Delay 2.5 ns —
Internal Performance 167 MHz —
Process Technology 0.22 µm CMOS —
Core Supply Voltage 2.5 V 2.5 V
Logic Family CMOS, SRAM-based APEX 20K
Packhaging 672-pin FC-FBGA 672-ball FC-FBGA (Fine-pitch Chip-Scale BGA)
Package Code BGA —
Number of Terminals 672 —
Terminal Form Ball (BGA) —
Speed Grade -3 (commercial fastest) -3X
Temperature na Operasyon 0 °C to 85 °C 0 °C to 85 °C (commercial)
Uri ng Pagpapasok Surface Mount Surface Mount (BGA)
Architecture MultiCore (LUT + Embedded System Blocks) MultiCore (LUT + embedded CAM/RAM)
Programming Method SRAM, JTAG (ByteBlaster) —
Katayuan ng Lifecycle Obsolete / Legacy —
Tindminan RoHS [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS compliance]
Device Sub-family — EP20K400
Technology — CMOS 0.22 µm
Number of Gates — 400,000 (typical)
Logic Cells — 16,640
Macros / Macrocells — 1664
User I/Os — 502
Dedicated I/O Lines — 496
Maksimum na Taktiko ng Oras — 181.82 MHz
Typical Propagation Delay — 2.07 ns
Programming Interface — JTAG (IEEE 1149.1) / ByteBlaster / MasterBlaster

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