EP20K400FC672-3 vs EP20K400FC672-3X 比較
詳細並排比較 EP20K400FC672-3 由 Altera 與 EP20K400FC672-3X 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP20K400FC672-3 | EP20K400FC672-3X |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | 最後購買 |
| Family | APEX 20K | — |
| Device Logic Elements | 16,640 cells | — |
| Typical Gate Count | 400,000 system gates | — |
| Maximum User I/Os | 502 | — |
| Propagation Delay | 2.5 ns | — |
| Internal Performance | 167 MHz | — |
| Process Technology | 0.22 µm CMOS | — |
| Core Supply Voltage | 2.5 V | 2.5 V |
| Logic Family | CMOS, SRAM-based | APEX 20K |
| 封裝 | 672-pin FC-FBGA | 672-ball FC-FBGA (Fine-pitch Chip-Scale BGA) |
| Package Code | BGA | — |
| Number of Terminals | 672 | — |
| Terminal Form | Ball (BGA) | — |
| Speed Grade | -3 (commercial fastest) | -3X |
| 工作溫度 | 0 °C to 85 °C | 0 °C to 85 °C (commercial) |
| 安裝類型 | Surface Mount | Surface Mount (BGA) |
| Architecture | MultiCore (LUT + Embedded System Blocks) | MultiCore (LUT + embedded CAM/RAM) |
| Programming Method | SRAM, JTAG (ByteBlaster) | — |
| 生命週期狀態 | Obsolete / Legacy | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS compliance] |
| Device Sub-family | — | EP20K400 |
| Technology | — | CMOS 0.22 µm |
| Number of Gates | — | 400,000 (typical) |
| Logic Cells | — | 16,640 |
| Macros / Macrocells | — | 1664 |
| User I/Os | — | 502 |
| Dedicated I/O Lines | — | 496 |
| 最大時脈頻率 | — | 181.82 MHz |
| Typical Propagation Delay | — | 2.07 ns |
| Programming Interface | — | JTAG (IEEE 1149.1) / ByteBlaster / MasterBlaster |