EP2A25F672ES vs EP2A25F672C9 Comparison
Detailed side-by-side comparison of EP2A25F672ES by Altera and EP2A25F672C9 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EP2A25F672ES
EP2A25F672ES - APEX II 25K Logic Elements FPGA | Altera | 672-BGA
EP2A25F672ES ObsoleteSpecification Comparison
| Parameter | EP2A25F672ES | EP2A25F672C9 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Nrnd |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $198.00 | $700.00 |
| Family | APEX II | APEX II |
| Logic Elements | 24,320 | β |
| Maximum Gates | 900,000 | β |
| Embedded System Blocks (ESBs) | 24 | β |
| Maximum Embedded RAM | 1.4 Mbit | β |
| Maximum User I/O Pins | 492 | β |
| Package | 672-ball FC-FBGA | 672-ball FCBGA (FineLine BGA) |
| Process Technology | 0.15 Β΅m CMOS | 0.15 Β΅m all-layer copper, up to 8 metal layers |
| Core Voltage | 1.5 V | β |
| Maximum System Clock Frequency | 500 MHz | β |
| Number of PLLs | 4 | β |
| I/O Banks | 16 | β |
| Supported I/O Standards | LVTTL, LVCMOS, PCI, LVDS, LVPECL, HSTL | β |
| Configuration Mode | Serial / Parallel / JTAG | β |
| Operating Temperature Range | [DATA_NEEDED: operating temperature range] | β |
| RoHS Status | Compliant | [DATA_NEEDED] |
| Logic Elements (LE) | β | Approximately 25,000 |
| Macro Cells | β | 2432 |
| User I/O | β | 492 |
| Package Dimensions | β | 27 mm x 27 mm |
| Ball Pitch | β | 1.0 mm |
| Logic Family | β | CMOS |
| Propagation Delay | β | 1.69 ns |
| Operating Temperature | β | 0Β°C to 85Β°C (Commercial) |
| Supply Voltage | β | [DATA_NEEDED: core VCC voltage] |
| I/O Standards | β | LVTTL, LVCMOS, PCI, LVDS, HSTL, SSTL (multi-voltage 1.5/1.8/2.5/3.3 V) |
| Configuration | β | Passive Serial, Passive Parallel Synchronous, JTAG |
| Embedded Memory | β | ESBs for dual-port RAM, ROM, FIFO |
| Mounting Type | β | Surface Mount |