EP2A25F672ES vs EP2A25F672C9 比較
詳細並排比較 EP2A25F672ES 由 Altera 與 EP2A25F672C9 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP2A25F672ES | EP2A25F672C9 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | NRND |
| Family | APEX II | APEX II |
| Logic Elements | 24,320 | — |
| Maximum Gates | 900,000 | — |
| Embedded System Blocks (ESBs) | 24 | — |
| Maximum Embedded RAM | 1.4 Mbit | — |
| Maximum User I/O Pins | 492 | — |
| 封裝 | 672-ball FC-FBGA | 672-ball FCBGA (FineLine BGA) |
| Process Technology | 0.15 µm CMOS | 0.15 µm all-layer copper, up to 8 metal layers |
| Core Voltage | 1.5 V | — |
| Maximum System Clock Frequency | 500 MHz | — |
| Number of PLLs | 4 | — |
| I/O Banks | 16 | — |
| Supported I/O Standards | LVTTL, LVCMOS, PCI, LVDS, LVPECL, HSTL | — |
| Configuration Mode | Serial / Parallel / JTAG | — |
| 工作溫度範圍 | [DATA_NEEDED: operating temperature range] | — |
| RoHS 狀態 | Compliant | [DATA_NEEDED] |
| Logic Elements (LE) | — | Approximately 25,000 |
| Macro Cells | — | 2432 |
| User I/O | — | 492 |
| Package Dimensions | — | 27 mm x 27 mm |
| Ball Pitch | — | 1.0 mm |
| Logic Family | — | CMOS |
| Propagation Delay | — | 1.69 ns |
| 工作溫度 | — | 0°C to 85°C (Commercial) |
| 供應電壓 | — | [DATA_NEEDED: core VCC voltage] |
| I/O Standards | — | LVTTL, LVCMOS, PCI, LVDS, HSTL, SSTL (multi-voltage 1.5/1.8/2.5/3.3 V) |
| Configuration | — | Passive Serial, Passive Parallel Synchronous, JTAG |
| Embedded Memory | — | ESBs for dual-port RAM, ROM, FIFO |
| 安裝類型 | — | Surface Mount |