EP610DC-30 vs EP610DM-35 Comparison
Detailed side-by-side comparison of EP610DC-30 by Altera and EP610DM-35 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP610DC-30 | EP610DM-35 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | NRND | Obsolete |
| Product Type | Classic EPLD (Erasable Programmable Logic Device) | — |
| Family | EP610 (Classic Device Family) | — |
| Macrocells | 16 | — |
| Logic Expanders | 4 (4 product terms per macrocell) | — |
| Usable Gates | 300 | — |
| Maximum Pipelined Clock Frequency | 100 MHz | — |
| Propagation Delay (tPD) | 30 ns | 35 ns |
| Dedicated Inputs | 16 | — |
| I/O Pins | 16 (with output enable) | 24 dedicated I/O (input + bidirectional) |
| Package | 24-pin CERDIP (windowed) | 24-pin CDIP (CERDIP) with UV window |
| Mounting Type | Through-Hole | — |
| Speed Grade | -30 (30 ns tPD) | — |
| Technology | CMOS EPROM | — |
| Programmability | UV-erasable, windowed EPROM | UV-erasable, reprogrammable |
| Security Bit | Yes (protects design after programming) | — |
| Output Modes | Registered and Combinatorial | — |
| Operating Temperature | Commercial (0C to +70C) | — |
| Manufacturer | — | Altera (Rochester Electronics authorized stock) |
| Part Family | — | Classic EPLD |
| Logic Family | — | PAL-type EPLD, CMOS, UV-erasable |
| Number of Macrocells | — | 16 |
| Number of Gates | — | 300 |
| Pipelined Data Rate (fMAX) | — | 100 MHz |
| Supply Voltage (VCC) | — | 5 V (single supply) |
| Temperature Grade (M) | — | Military -55°C to +125°C |
| Operating Temperature Range | — | -55°C to +125°C |
| MSL Level | — | [DATA_NEEDED: MSL rating] |
| RoHS Status | — | Non-compliant (contains lead, hermetic CERDIP) |