EP610DC-30 vs EP610DM-35 Perbandingan

Perbandingan bersamaan detil EP610DC-30 dari Altera dan EP610DM-35 dari Altera. Bandingkan spesifikasi penting, parameter listrik, pengemasan, status cycle, harga, dan ketersediaan untuk menentukan komponen terbaik untuk kebutuhan desain Anda.

Perbandingan Spesifikasi

Parameter Umum EP610DC-30 EP610DM-35
Merek Altera Altera
Kategori FPGA & CPLD FPGA & CPLD
Status Lingkungan Hidup NRND Obsolete
Product Type Classic EPLD (Erasable Programmable Logic Device) —
Family EP610 (Classic Device Family) —
Macrocells 16 —
Logic Expanders 4 (4 product terms per macrocell) —
Usable Gates 300 —
Maximum Pipelined Clock Frequency 100 MHz —
Propagation Delay (tPD) 30 ns 35 ns
Dedicated Inputs 16 —
I/O Pins 16 (with output enable) 24 dedicated I/O (input + bidirectional)
Paket 24-pin CERDIP (windowed) 24-pin CDIP (CERDIP) with UV window
Tipe Mounting Through-Hole —
Speed Grade -30 (30 ns tPD) —
Technology CMOS EPROM —
Programmability UV-erasable, windowed EPROM UV-erasable, reprogrammable
Security Bit Yes (protects design after programming) —
Output Modes Registered and Combinatorial —
Suhu Kerja Commercial (0C to +70C) —
Manufacturer — Altera (Rochester Electronics authorized stock)
Part Family — Classic EPLD
Logic Family — PAL-type EPLD, CMOS, UV-erasable
Number of Macrocells — 16
Number of Gates — 300
Pipelined Data Rate (fMAX) — 100 MHz
Supply Voltage (VCC) — 5 V (single supply)
Temperature Grade (M) — Military -55°C to +125°C
Rentang Suhu Kerja — -55°C to +125°C
Level MSL — [DATA_NEEDED: MSL rating]
Status RoHS — Non-compliant (contains lead, hermetic CERDIP)

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