EP610IDC-10 vs EP610DC-10 比較
詳細並排比較 EP610IDC-10 由 Intel 與 EP610DC-10 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP610IDC-10 | EP610DC-10 |
|---|---|---|
| 品牌 | Intel | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Device Family | Altera Classic EPLD | Altera Classic EPLD |
| Logic Capacity | 300 usable gates | — |
| Macrocell Count | 16 macrocells | — |
| Pin-to-Pin Logic Delay (tpd) | 10 ns | — |
| Maximum Counter Frequency (fCNT) | 100 MHz | — |
| Supply Voltage (VCC) | 5 V (nominal) | — |
| I/O Logic Compatibility | 100% TTL emulation | — |
| Technology | CMOS, UV-erasable (windowed ceramic) | CMOS, EPROM-based (UV-erasable) |
| Package Type | 24-pin Ceramic DIP (CDIP) | — |
| Dedicated Inputs | 4 | — |
| I/O Pins | 20 | [DATA_NEEDED: exact I/O count for CDIP-24 variant] |
| 工作溫度範圍 | 0 °C to +70 °C (commercial) | — |
| Programmable Interconnect | Yes (on-chip) | — |
| In-System Programmability | Yes (via MAX+PLUS II) | — |
| Boundary-Scan Test | Yes (per device documentation) | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS status of CDIP-10 variant] | [DATA_NEEDED: not stated in verified web data] |
| 安裝類型 | Through-hole | Through-Hole |
| Macrocells | — | 16 |
| Maximum Pipelined Data Rate | — | 100 MHz |
| Pin-to-Pin Propagation Delay (tpd) | — | 10 ns |
| Speed Grade | — | -10 |
| 封裝 | — | 24-pin CDIP (Ceramic DIP, windowed) |
| 供應電壓 | — | 5 V (single supply) |
| 工作溫度 | — | 0C to +70C (commercial) |
| Logic Elements | — | 16 macrocells (programmable AND/OR array) |
| Configuration Memory | — | UV-erasable EPROM |
| Reprogrammable | — | Yes (UV erase window on package) |