EP910DI-30 vs EP910IDI-15 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP910DI-30 sa pamamagitan ng Rochester Electronics at EP910IDI-15 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Rochester Electronics
EP910DI-30 - 24-Macrocell EPLD, 30ns, CDIP-40 | Altera (Rochester)
EP910DI-30 NrndPagsanggunian na paghahambing
| Parametro | EP910DI-30 | EP910IDI-15 |
|---|---|---|
| Brand | Rochester Electronics | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | NRND | Obsolete |
| Product Type | UV-Erasable Programmable Logic Device (EPLD) | — |
| Family | Classic EPLD (Altera EP910 series) | Classic EPLD |
| Macrocell Count | 24 | — |
| Propagation Delay (tpd) | 30 ns | — |
| Maximum Toggle Frequency (fmax) | 62 MHz | — |
| Supply Voltage (VCC) | 5 V (single supply) | — |
| Technology | CMOS, UV-erasable EPROM | CMOS EPROM |
| Packhaging | CDIP-40 (ceramic DIP, 40-pin with UV window) | 40-pin CDIP (CerDIP) with quartz window |
| Uri ng Pagpapasok | Through-Hole (DIP) | Through-hole (DIP) |
| Dedicated Inputs | 10 | — |
| Dedicated I/O Pins | 12 (12 input + 12 output) | — |
| Output Enable Pins | 2 | — |
| Bilang ng Pin | 40 | — |
| Programmable Logic Element | JEDEC fuse map (3rd-party programmer) | — |
| Temperature na Operasyon | -40C to +85C (industrial) | -40C to +85C (industrial, "I" grade) |
| Tindminan RoHS | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS compliance of CDIP windowed part] |
| Manufacturer (Original) | Altera (now Intel PSG) | — |
| Current Distributor / Authorized Aftermarket | Rochester Electronics, LLC | — |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Logic Gates | — | 450 gates |
| Macrocells | — | 24 |
| Maximum User I/O Pins | — | 36 |
| Pin-to-Pin Propagation Delay (tpd) | — | 15 ns |
| Maximum Counter Frequency | — | 66.6 MHz |
| Supply Voltage (Vcc) | — | 5 V |
| Program/Erase Method | — | UV-erasable windowed CerDIP |
| Macrocells Configurable As | — | D, T, JK, SR flip-flop, or combinatorial |
| Development Tool | — | MAX+PLUS II (legacy) / Altera Classic compiler |
| Programming Hardware | — | Altera Logic Programmer card |
| Logic Family Compatibility | — | Pin-, function-, and JEDEC-map compatible across all EP910 speed grades and packages |