EP910DI-30 vs EP910IDI-15 比較

詳細並排比較 EP910DI-30 由 Rochester Electronics 與 EP910IDI-15 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

規格比較

參數 EP910DI-30 EP910IDI-15
品牌 Rochester Electronics Altera
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 NRND Obsolete
Product Type UV-Erasable Programmable Logic Device (EPLD) —
Family Classic EPLD (Altera EP910 series) Classic EPLD
Macrocell Count 24 —
Propagation Delay (tpd) 30 ns —
Maximum Toggle Frequency (fmax) 62 MHz —
Supply Voltage (VCC) 5 V (single supply) —
Technology CMOS, UV-erasable EPROM CMOS EPROM
封裝 CDIP-40 (ceramic DIP, 40-pin with UV window) 40-pin CDIP (CerDIP) with quartz window
安裝類型 Through-Hole (DIP) Through-hole (DIP)
Dedicated Inputs 10 —
Dedicated I/O Pins 12 (12 input + 12 output) —
Output Enable Pins 2 —
腳位數 40 —
Programmable Logic Element JEDEC fuse map (3rd-party programmer) —
工作溫度 -40C to +85C (industrial) -40C to +85C (industrial, "I" grade)
RoHS 狀態 [DATA_NEEDED: RoHS compliance status] [DATA_NEEDED: RoHS compliance of CDIP windowed part]
Manufacturer (Original) Altera (now Intel PSG) —
Current Distributor / Authorized Aftermarket Rochester Electronics, LLC —
Device Type — CPLD (Complex Programmable Logic Device)
Logic Gates — 450 gates
Macrocells — 24
Maximum User I/O Pins — 36
Pin-to-Pin Propagation Delay (tpd) — 15 ns
Maximum Counter Frequency — 66.6 MHz
Supply Voltage (Vcc) — 5 V
Program/Erase Method — UV-erasable windowed CerDIP
Macrocells Configurable As — D, T, JK, SR flip-flop, or combinatorial
Development Tool — MAX+PLUS II (legacy) / Altera Classic compiler
Programming Hardware — Altera Logic Programmer card
Logic Family Compatibility — Pin-, function-, and JEDEC-map compatible across all EP910 speed grades and packages

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