EP910DM-40 vs EP910DM883B Comparison
Detailed side-by-side comparison of EP910DM-40 by Altera and EP910DM883B by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP910DM-40 | EP910DM883B |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Product Type | UV Erasable Programmable Logic Device (EPLD) | — |
| Family | Altera Classic EP910 | Classic EPLD - EP910 Series |
| Architecture | PAL-type AND/OR with global programmable interconnect bus | PAL-type AND-OR-NOT, CMOS |
| Macrocells | 24 | 24 |
| Dedicated Inputs | 36 | — |
| Dedicated Outputs | 24 | — |
| Bidirectional I/O Lines | 24 | — |
| Product Terms | 240 | 240 |
| Propagation Delay (tPD) | 40 ns | 40 ns (typical) |
| External Clocks | 2 | — |
| Process Technology | CMOS | — |
| Package | 40-pin Ceramic DIP (Cerdip) with UV window | CDIP-40 (Ceramic DIP, 40-pin) |
| Mounting Type | Through-Hole (DIP) | Through-Hole (DIP) |
| Operating Temperature | [DATA_NEEDED: operating temperature range] | -55 °C to +125 °C (military) |
| Supply Voltage | 5 V | — |
| RoHS Status | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS status] |
| Programming Interface | JEDEC-standard fuse-map / UV erasure | — |
| Manufacturer | — | Altera (now part of Intel) |
| Device Type | — | Erasable Programmable Logic Device (EPLD) |
| Inputs | — | 36 |
| Outputs | — | 24 |
| Maximum Clock Frequency | — | 25 MHz |
| Supply Voltage (VCC) | — | 5 V |
| Programming Voltage (VPP) | — | 12.5 V (UV-erase window) |
| MIL Processing | — | MIL-STD-883B Class B |
| Configuration Memory | — | UV-erasable EPROM |
| Logic Elements | — | Combinational + Registered |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |