EP910DM-40 vs EP910DM883B Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP910DM-40 sa pamamagitan ng Altera at EP910DM883B sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP910DM-40 | EP910DM883B |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Product Type | UV Erasable Programmable Logic Device (EPLD) | — |
| Family | Altera Classic EP910 | Classic EPLD - EP910 Series |
| Architecture | PAL-type AND/OR with global programmable interconnect bus | PAL-type AND-OR-NOT, CMOS |
| Macrocells | 24 | 24 |
| Dedicated Inputs | 36 | — |
| Dedicated Outputs | 24 | — |
| Bidirectional I/O Lines | 24 | — |
| Product Terms | 240 | 240 |
| Propagation Delay (tPD) | 40 ns | 40 ns (typical) |
| External Clocks | 2 | — |
| Process Technology | CMOS | — |
| Packhaging | 40-pin Ceramic DIP (Cerdip) with UV window | CDIP-40 (Ceramic DIP, 40-pin) |
| Uri ng Pagpapasok | Through-Hole (DIP) | Through-Hole (DIP) |
| Temperature na Operasyon | [DATA_NEEDED: operating temperature range] | -55 °C to +125 °C (military) |
| Volte ng Pagbibigay | 5 V | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS status] |
| Programming Interface | JEDEC-standard fuse-map / UV erasure | — |
| Manufacturer | — | Altera (now part of Intel) |
| Device Type | — | Erasable Programmable Logic Device (EPLD) |
| Inputs | — | 36 |
| Outputs | — | 24 |
| Maksimum na Taktiko ng Oras | — | 25 MHz |
| Supply Voltage (VCC) | — | 5 V |
| Programming Voltage (VPP) | — | 12.5 V (UV-erase window) |
| MIL Processing | — | MIL-STD-883B Class B |
| Configuration Memory | — | UV-erasable EPROM |
| Logic Elements | — | Combinational + Registered |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |