EP910DM-40 vs EP910DM883B 比較
詳細並排比較 EP910DM-40 由 Altera 與 EP910DM883B 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP910DM-40 | EP910DM883B |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Product Type | UV Erasable Programmable Logic Device (EPLD) | — |
| Family | Altera Classic EP910 | Classic EPLD - EP910 Series |
| Architecture | PAL-type AND/OR with global programmable interconnect bus | PAL-type AND-OR-NOT, CMOS |
| Macrocells | 24 | 24 |
| Dedicated Inputs | 36 | — |
| Dedicated Outputs | 24 | — |
| Bidirectional I/O Lines | 24 | — |
| Product Terms | 240 | 240 |
| Propagation Delay (tPD) | 40 ns | 40 ns (typical) |
| External Clocks | 2 | — |
| Process Technology | CMOS | — |
| 封裝 | 40-pin Ceramic DIP (Cerdip) with UV window | CDIP-40 (Ceramic DIP, 40-pin) |
| 安裝類型 | Through-Hole (DIP) | Through-Hole (DIP) |
| 工作溫度 | [DATA_NEEDED: operating temperature range] | -55 °C to +125 °C (military) |
| 供應電壓 | 5 V | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS status] |
| Programming Interface | JEDEC-standard fuse-map / UV erasure | — |
| Manufacturer | — | Altera (now part of Intel) |
| Device Type | — | Erasable Programmable Logic Device (EPLD) |
| Inputs | — | 36 |
| Outputs | — | 24 |
| 最大時脈頻率 | — | 25 MHz |
| Supply Voltage (VCC) | — | 5 V |
| Programming Voltage (VPP) | — | 12.5 V (UV-erase window) |
| MIL Processing | — | MIL-STD-883B Class B |
| Configuration Memory | — | UV-erasable EPROM |
| Logic Elements | — | Combinational + Registered |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |