EP910IPC-50 vs EP910LI-20 Comparison

Detailed side-by-side comparison of EP910IPC-50 by Altera and EP910LI-20 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EP910IPC-50 EP910LI-20
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $13.85 $19.95
Product Type Erasable Programmable Logic Device (EPLD) β€”
Family Altera Classic EPLD Altera Classic EPLD
Logic Capacity [DATA_NEEDED: macrocell count / equivalent gates] β€”
Propagation Delay (tPD) 50 ns β€”
Clock-to-Output (tCO) 35 ns β€”
Maximum Toggle Frequency [DATA_NEEDED: fMAX] β€”
User I/O Pins 24 β€”
Package 40-pin Ceramic DIP (IPC, windowed) 40-pin Ceramic DIP (Windowed)
Supply Voltage (VCC) 4.75 V to 5.25 V (5 V nominal) 5 V
Operating Temperature -40C to +85C (industrial) -40C to +85C (Industrial)
Technology CMOS EPROM cell CMOS, UV-erasable
Programming Method Off-board EPROM programmer + UV erase β€”
Erasure Method UV light through ceramic window (IPC package) β€”
Mounting Type Through-Hole (DIP) β€”
RoHS Status [DATA_NEEDED: not stated in verified data] [DATA_NEEDED: RoHS status]
Macrocells β€” 24
Maximum Operating Frequency β€” 62 MHz
Propagation Delay (tpd) β€” 20 ns
Dedicated Inputs β€” 16
I/O Pins β€” 24
Package Type β€” Through-Hole, Ceramic DIP with Quartz Window
Temperature Grade β€” Industrial (-40C to +85C)
Pin Count β€” 40
Logic Family β€” EPLD (Erasable PLD)
Architecture β€” Sum-of-products macrocell
Pin/Package Compatibility β€” Pin-compatible across EP910 family

Datasheets & Resources

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