EP910IPC-50 vs EP910LI-20 Perbandingan

Perbandingan bersamaan detil EP910IPC-50 dari Altera dan EP910LI-20 dari Altera. Bandingkan spesifikasi penting, parameter listrik, pengemasan, status cycle, harga, dan ketersediaan untuk menentukan komponen terbaik untuk kebutuhan desain Anda.

Perbandingan Spesifikasi

Parameter Umum EP910IPC-50 EP910LI-20
Merek Altera Altera
Kategori FPGA & CPLD FPGA & CPLD
Status Lingkungan Hidup Obsolete Obsolete
Product Type Erasable Programmable Logic Device (EPLD) —
Family Altera Classic EPLD Altera Classic EPLD
Logic Capacity [DATA_NEEDED: macrocell count / equivalent gates] —
Propagation Delay (tPD) 50 ns —
Clock-to-Output (tCO) 35 ns —
Maximum Toggle Frequency [DATA_NEEDED: fMAX] —
User I/O Pins 24 —
Paket 40-pin Ceramic DIP (IPC, windowed) 40-pin Ceramic DIP (Windowed)
Supply Voltage (VCC) 4.75 V to 5.25 V (5 V nominal) 5 V
Suhu Kerja -40C to +85C (industrial) -40C to +85C (Industrial)
Technology CMOS EPROM cell CMOS, UV-erasable
Programming Method Off-board EPROM programmer + UV erase —
Erasure Method UV light through ceramic window (IPC package) —
Tipe Mounting Through-Hole (DIP) —
Status RoHS [DATA_NEEDED: not stated in verified data] [DATA_NEEDED: RoHS status]
Macrocells — 24
Maximum Operating Frequency — 62 MHz
Propagation Delay (tpd) — 20 ns
Dedicated Inputs — 16
I/O Pins — 24
Package Type — Through-Hole, Ceramic DIP with Quartz Window
Temperature Grade — Industrial (-40C to +85C)
Jumlah Pin — 40
Logic Family — EPLD (Erasable PLD)
Architecture — Sum-of-products macrocell
Pin/Package Compatibility — Pin-compatible across EP910 family

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