EP910IPC-50 vs EP910LI-20 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP910IPC-50 sa pamamagitan ng Altera at EP910LI-20 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP910IPC-50 | EP910LI-20 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Product Type | Erasable Programmable Logic Device (EPLD) | — |
| Family | Altera Classic EPLD | Altera Classic EPLD |
| Logic Capacity | [DATA_NEEDED: macrocell count / equivalent gates] | — |
| Propagation Delay (tPD) | 50 ns | — |
| Clock-to-Output (tCO) | 35 ns | — |
| Maximum Toggle Frequency | [DATA_NEEDED: fMAX] | — |
| User I/O Pins | 24 | — |
| Packhaging | 40-pin Ceramic DIP (IPC, windowed) | 40-pin Ceramic DIP (Windowed) |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) | 5 V |
| Temperature na Operasyon | -40C to +85C (industrial) | -40C to +85C (Industrial) |
| Technology | CMOS EPROM cell | CMOS, UV-erasable |
| Programming Method | Off-board EPROM programmer + UV erase | — |
| Erasure Method | UV light through ceramic window (IPC package) | — |
| Uri ng Pagpapasok | Through-Hole (DIP) | — |
| Tindminan RoHS | [DATA_NEEDED: not stated in verified data] | [DATA_NEEDED: RoHS status] |
| Macrocells | — | 24 |
| Maximum Operating Frequency | — | 62 MHz |
| Propagation Delay (tpd) | — | 20 ns |
| Dedicated Inputs | — | 16 |
| I/O Pins | — | 24 |
| Package Type | — | Through-Hole, Ceramic DIP with Quartz Window |
| Temperature Grade | — | Industrial (-40C to +85C) |
| Bilang ng Pin | — | 40 |
| Logic Family | — | EPLD (Erasable PLD) |
| Architecture | — | Sum-of-products macrocell |
| Pin/Package Compatibility | — | Pin-compatible across EP910 family |