EP910LC-32 vs EP910LC-30Y Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP910LC-32 sa pamamagitan ng Altera at EP910LC-30Y sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EP910LC-32 EP910LC-30Y
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete NRND
Device Family Altera Classic EPLD —
Number of Macrocells 24 —
Number of Usable Gates 900 gates (typical) —
Number of Dedicated Inputs 10 —
Number of I/O Pins 20 —
Packhaging PLCC-32 PLCC-44
Speed Grade -32 —
Maximum Toggle Frequency (fMAX) [DATA_NEEDED: fMAX value in MHz for -32 grade] —
Pin-to-Pin Propagation Delay (tPD) [DATA_NEEDED: tPD in ns for -32 grade] —
Supply Voltage (VCC) 5 V —
Logic Family Low-power CMOS (LC suffix) —
Programming Method UV-erasable or one-time programmable (OTP for LC windowless variant) —
Hanay ng Temperature na Operasyon [DATA_NEEDED: commercial or industrial grade] —
I/O Standard TTL-compatible —
Uri ng Pagpapasok Surface Mount (PLCC socket or direct solder) Surface Mount (PLCC socket)
Tindminan RoHS unknown [DATA_NEEDED: RoHS status not specified in retrieved data]
Level ng MSL unknown —
Family — Altera Classic EPLD
Device Type — EPLD (Erasable Programmable Logic Device)
Macrocells — 24
Usable Gates — 450
Pin-to-Pin Delay (tPD) — 30 ns
Counter Frequency (fMAX) — 100 MHz (family maximum)
Volte ng Pagbibigay — 5 V (TTL-compatible)
Process Technology — CMOS, UV-erasable / OTP
Temperature na Operasyon — Commercial 0C to +70C
Speed/Power Grade — LC (low-power, 30ns)
Processing Flow — Y (extended reliability)
Logic Compatibility — 100% TTL emulation

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