EP910PI-12T vs EP910PI-15T Comparison
Detailed side-by-side comparison of EP910PI-12T by Altera and EP910PI-15T by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP910PI-12T | EP910PI-15T |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Nrnd | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $9.95 | $10.95 |
| Family | Altera Classic EPLD | Altera Classic EPLD (EP910 series) |
| Macrocells | 24 | 24 |
| Propagation Delay (tPD) | 12 ns | 15 ns max (speed grade -15) |
| Maximum Operating Frequency | 76.9 MHz | β |
| Logic Gates | [DATA_NEEDED: logic gate count] | β |
| Supply Voltage (VCC) | 5 V (4.75 V min, 5.25 V max) | β |
| I/O Pins | 24 | 24 |
| Dedicated Inputs | 12 | 12 |
| External Clock Inputs | 2 | β |
| Outputs | 24 | β |
| Terminals / Pin Count | 44 (PDIP-40 package pinout with NC pins) | β |
| Package | 40-pin PDIP (Plastic DIP) | 40-pin PDIP (Plastic DIP, R-PDIP-T40) |
| Process Technology | CMOS | β |
| Operating Temperature | 0C to +70C (commercial) | [DATA_NEEDED: industrial/commercial temp range] |
| Programmable Technology | UV-erasable EPROM | β |
| Programming Interface | JEDEC-standard | β |
| RoHS Status | Non-compliant (legacy PDIP package, contains lead) | [DATA_NEEDED: original Altera part; likely non-RoHS as 5V PDIP] |
| Lifecycle Status | NRND / EOL (mature legacy product) | β |
| Product Type | β | Classic EPLD (Erasable Programmable Logic Device) |
| Logic Blocks | β | 6 LABs of 4 macrocells each (Classic architecture) |
| Supply Voltage | β | 4.5 V to 5.5 V (5 V nominal) |
| Technology | β | CMOS EEPROM (electrically erasable) |
| Mounting Type | β | Through-Hole |
| Output Drive Current | β | [DATA_NEEDED: per-pin DC output current, mA] |
| Programming | β | JEDEC-standard, serial/parallel programmer |