EP910PI-12T vs EP910PI-15T Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP910PI-12T sa pamamagitan ng Altera at EP910PI-15T sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EP910PI-12T EP910PI-15T
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle NRND Obsolete
Family Altera Classic EPLD Altera Classic EPLD (EP910 series)
Macrocells 24 24
Propagation Delay (tPD) 12 ns 15 ns max (speed grade -15)
Maximum Operating Frequency 76.9 MHz —
Logic Gates [DATA_NEEDED: logic gate count] —
Supply Voltage (VCC) 5 V (4.75 V min, 5.25 V max) —
I/O Pins 24 24
Dedicated Inputs 12 12
External Clock Inputs 2 —
Outputs 24 —
Terminals / Pin Count 44 (PDIP-40 package pinout with NC pins) —
Packhaging 40-pin PDIP (Plastic DIP) 40-pin PDIP (Plastic DIP, R-PDIP-T40)
Process Technology CMOS —
Temperature na Operasyon 0C to +70C (commercial) [DATA_NEEDED: industrial/commercial temp range]
Programmable Technology UV-erasable EPROM —
Programming Interface JEDEC-standard —
Tindminan RoHS Non-compliant (legacy PDIP package, contains lead) [DATA_NEEDED: original Altera part; likely non-RoHS as 5V PDIP]
Katayuan ng Lifecycle NRND / EOL (mature legacy product) —
Product Type — Classic EPLD (Erasable Programmable Logic Device)
Logic Blocks — 6 LABs of 4 macrocells each (Classic architecture)
Volte ng Pagbibigay — 4.5 V to 5.5 V (5 V nominal)
Technology — CMOS EEPROM (electrically erasable)
Uri ng Pagpapasok — Through-Hole
Output Drive Current — [DATA_NEEDED: per-pin DC output current, mA]
Programming — JEDEC-standard, serial/parallel programmer

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