EP910PI-12T vs EP910PI-15T Pengandingan
Pengandingan Sisi Kiri Sisi Kanan Terperinci EP910PI-12T disebabkan oleh Altera dan EP910PI-15T disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.
Pengandingan Spesifikasi
| Parametr | EP910PI-12T | EP910PI-15T |
|---|---|---|
| Merek | Altera | Altera |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | NRND | Obsolete |
| Family | Altera Classic EPLD | Altera Classic EPLD (EP910 series) |
| Macrocells | 24 | 24 |
| Propagation Delay (tPD) | 12 ns | 15 ns max (speed grade -15) |
| Maximum Operating Frequency | 76.9 MHz | — |
| Logic Gates | [DATA_NEEDED: logic gate count] | — |
| Supply Voltage (VCC) | 5 V (4.75 V min, 5.25 V max) | — |
| I/O Pins | 24 | 24 |
| Dedicated Inputs | 12 | 12 |
| External Clock Inputs | 2 | — |
| Outputs | 24 | — |
| Terminals / Pin Count | 44 (PDIP-40 package pinout with NC pins) | — |
| Kemasan | 40-pin PDIP (Plastic DIP) | 40-pin PDIP (Plastic DIP, R-PDIP-T40) |
| Process Technology | CMOS | — |
| Suhu Operasi | 0C to +70C (commercial) | [DATA_NEEDED: industrial/commercial temp range] |
| Programmable Technology | UV-erasable EPROM | — |
| Programming Interface | JEDEC-standard | — |
| Status RoHS | Non-compliant (legacy PDIP package, contains lead) | [DATA_NEEDED: original Altera part; likely non-RoHS as 5V PDIP] |
| Status Lingkungan Hidup | NRND / EOL (mature legacy product) | — |
| Product Type | — | Classic EPLD (Erasable Programmable Logic Device) |
| Logic Blocks | — | 6 LABs of 4 macrocells each (Classic architecture) |
| Tegangan Pemberi Arus | — | 4.5 V to 5.5 V (5 V nominal) |
| Technology | — | CMOS EEPROM (electrically erasable) |
| Jenis Pemasangan | — | Through-Hole |
| Output Drive Current | — | [DATA_NEEDED: per-pin DC output current, mA] |
| Programming | — | JEDEC-standard, serial/parallel programmer |