EPC2L120N vs EPC2L20N Pengandingan

Pengandingan Sisi Kiri Sisi Kanan Terperinci EPC2L120N disebabkan oleh Intel dan EPC2L20N disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.

Pengandingan Spesifikasi

Parametr EPC2L120N EPC2L20N
Merek Intel Altera
Kategori FPGA & CPLD Memory ICs
Status Lingkungan Hidup Obsolete NRND
Device Type Configuration Device for SRAM-based LUT FPGAs —
Manufacturer Intel (formerly Altera) —
Family EPC2 (Enhanced Configuration Device) —
Memory Capacity 165,888 bits (400,000 gates equivalent) —
Operating Voltage (VCCIO) 2.7 V to 3.6 V —
5V Tolerance Yes (5V-tolerant I/O) —
Configuration Clock (FPP) Up to 66 MHz —
Configuration Clock (PS) Up to 33 MHz —
Internal Oscillator 8 MHz with programmable divider —
JTAG Interface IEEE Std 1149.1 compliant, ISP support —
Programming Cycles 100,000 erase/program cycles —
Sector Erase Time [DATA_NEEDED: typical sector erase time] —
Kemasan 84-pin PLCC (J-Lead) —
Configuration Schemes FPP, PS, JTAG, daisy chain —
Suhu Operasi [DATA_NEEDED: industrial temp range] 0C to +70C (commercial)
Supported FPGA Families Cyclone, APEX, FLEX, Mercury, ACEX, Stratix Altera APEX, ACEX, Cyclone, FLEX 10K, Mercury (per datasheet)
Status RoHS unknown Compliant
Fungsi — In-System Programmable Configuration PROM for SRAM-based LUT FPGAs
Saiz Ingatan — 1.6 Mbit
Programmable Type — In System Programmable (ISP)
Supply Voltage - VCCINT/VCCIO — 3.0 V to 3.6 V or 4.5 V to 5.5 V
Kemasan / Case — 20-LCC (J-Lead), PLCC-20
Packaging — Tube
Configuration Interface — Serial (Altera FPP / PS configuration scheme)
Cascade Support — Yes (multi-PROM chain via CE control)
Programming Method — In-system via 4-wire ISP / JTAG-style
Jenis Pemasangan — Surface Mount (J-Lead PLCC)
Kiraan Pin — 20
Lead Finish — Matte Tin (Pb-free)
Aras MSL — 3 (168 hours)

Laporan Datasheet & Sumber

Lihat Semua Produk Buat BOQ Minta Bao Harga