EPC2LC20-T vs EPC2LI20 Comparison

Detailed side-by-side comparison of EPC2LC20-T by Altera and EPC2LI20 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Altera
EPC2LC20-T

EPC2LC20-T - 1.6Mb FPGA Config PROM PLCC-20 | Altera

EPC2LC20-T ⚠ Last Time Buy

Specification Comparison

Parameter EPC2LC20-T EPC2LI20
Brand Altera Altera
Category Memory ICs Memory ICs
Lifecycle Status Last_time_buy Nrnd
Stock Status In Stock In Stock
Unit Price (USD) $7.40 $5.95
Memory Type Configuration PROM (Flash) Flash (in-system programmable)
Memory Size 1.6 Mb 1.6 Mb (1,572,864 bits)
Configuration Mode Serial (PS mode), cascadable β€”
Max Configuration Frequency 10 MHz β€”
Supply Voltage 3.3 V (typical) β€”
Programmability In-System Programmable via JTAG β€”
JTAG Interface IEEE Std 1149.1-1990 compliant β€”
Supported FPGA Families ACEX, APEX, Cyclone, FLEX, MAX 7000A/B, MAX II, Mercury β€”
Cascade Support Yes (nCASC pin) β€”
Operating Temperature -40C to +85C (industrial) -40 C to +85 C (Industrial)
Package 20-PLCC (9x9 mm) β€”
Mounting Type Surface Mount Surface Mount (PLCC socket-compatible)
Packaging Suffix -T = Tape and Reel β€”
RoHS Status Compliant [DATA_NEEDED: RoHS status]
Lead-Free Yes β€”
Programmable Type β€” In System Programmable (ISP)
Function β€” Configuration PROM for SRAM-based FPGAs
Supply Voltage - Operating β€” 3.0 V to 3.6 V and 4.5 V to 5.5 V (auto-sensing)
Package / Case β€” 20-PLCC (J-lead, 9x9 mm)
Configuration Interface β€” Serial or Byte-wide (parallel)
Decompression β€” On-chip (supports compressed bitstreams)
JTAG / ISP Interface β€” IEEE 1532 (TCK, TMS, TDI, TDO)
Multi-Device Support β€” Yes (daisy-chain configuration)
User-Accessible Memory β€” Yes (unused flash available to user logic)
MSL Level β€” [DATA_NEEDED: MSL level]

Datasheets & Resources

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