EPC2LC20-T vs EPC2LI20 Comparison
Detailed side-by-side comparison of EPC2LC20-T by Altera and EPC2LI20 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPC2LC20-T | EPC2LI20 |
|---|---|---|
| Brand | Altera | Altera |
| Category | Memory ICs | Memory ICs |
| Lifecycle Status | Last Time Buy | NRND |
| Memory Type | Configuration PROM (Flash) | Flash (in-system programmable) |
| Memory Size | 1.6 Mb | 1.6 Mb (1,572,864 bits) |
| Configuration Mode | Serial (PS mode), cascadable | — |
| Max Configuration Frequency | 10 MHz | — |
| Supply Voltage | 3.3 V (typical) | — |
| Programmability | In-System Programmable via JTAG | — |
| JTAG Interface | IEEE Std 1149.1-1990 compliant | — |
| Supported FPGA Families | ACEX, APEX, Cyclone, FLEX, MAX 7000A/B, MAX II, Mercury | — |
| Cascade Support | Yes (nCASC pin) | — |
| Operating Temperature | -40C to +85C (industrial) | -40 C to +85 C (Industrial) |
| Package | 20-PLCC (9x9 mm) | — |
| Mounting Type | Surface Mount | Surface Mount (PLCC socket-compatible) |
| Packaging Suffix | -T = Tape and Reel | — |
| RoHS Status | Compliant | [DATA_NEEDED: RoHS status] |
| Lead-Free | Yes | — |
| Programmable Type | — | In System Programmable (ISP) |
| Function | — | Configuration PROM for SRAM-based FPGAs |
| Supply Voltage - Operating | — | 3.0 V to 3.6 V and 4.5 V to 5.5 V (auto-sensing) |
| Package / Case | — | 20-PLCC (J-lead, 9x9 mm) |
| Configuration Interface | — | Serial or Byte-wide (parallel) |
| Decompression | — | On-chip (supports compressed bitstreams) |
| JTAG / ISP Interface | — | IEEE 1532 (TCK, TMS, TDI, TDO) |
| Multi-Device Support | — | Yes (daisy-chain configuration) |
| User-Accessible Memory | — | Yes (unused flash available to user logic) |
| MSL Level | — | [DATA_NEEDED: MSL level] |