EPC2LC20-T vs EPC2LI20 比較
詳細並排比較 EPC2LC20-T 由 Altera 與 EPC2LI20 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPC2LC20-T | EPC2LI20 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | Memory ICs | Memory ICs |
| 生命週期狀態 | 最後購買 | NRND |
| 記憶體類型 | Configuration PROM (Flash) | Flash (in-system programmable) |
| 記憶體容量 | 1.6 Mb | 1.6 Mb (1,572,864 bits) |
| Configuration Mode | Serial (PS mode), cascadable | — |
| Max Configuration Frequency | 10 MHz | — |
| 供應電壓 | 3.3 V (typical) | — |
| Programmability | In-System Programmable via JTAG | — |
| JTAG Interface | IEEE Std 1149.1-1990 compliant | — |
| Supported FPGA Families | ACEX, APEX, Cyclone, FLEX, MAX 7000A/B, MAX II, Mercury | — |
| Cascade Support | Yes (nCASC pin) | — |
| 工作溫度 | -40C to +85C (industrial) | -40 C to +85 C (Industrial) |
| 封裝 | 20-PLCC (9x9 mm) | — |
| 安裝類型 | Surface Mount | Surface Mount (PLCC socket-compatible) |
| Packaging Suffix | -T = Tape and Reel | — |
| RoHS 狀態 | Compliant | [DATA_NEEDED: RoHS status] |
| Lead-Free | Yes | — |
| Programmable Type | — | In System Programmable (ISP) |
| 功能 | — | Configuration PROM for SRAM-based FPGAs |
| Supply Voltage - Operating | — | 3.0 V to 3.6 V and 4.5 V to 5.5 V (auto-sensing) |
| 封裝 / 外殼 | — | 20-PLCC (J-lead, 9x9 mm) |
| Configuration Interface | — | Serial or Byte-wide (parallel) |
| Decompression | — | On-chip (supports compressed bitstreams) |
| JTAG / ISP Interface | — | IEEE 1532 (TCK, TMS, TDI, TDO) |
| Multi-Device Support | — | Yes (daisy-chain configuration) |
| User-Accessible Memory | — | Yes (unused flash available to user logic) |
| MSL 等級 | — | [DATA_NEEDED: MSL level] |